1 /****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 */ 20 21 /*****************************************************************************/ 22 /* Includes */ 23 /*****************************************************************************/ 24 25 /* System include files */ 26 #include <stdio.h> 27 28 /* User include files */ 29 #include "irc_datatypes.h" 30 #include "irc_common.h" 31 #include "irc_cntrl_param.h" 32 #include "irc_mem_req_and_acq.h" 33 #include "irc_fixed_point_error_bits.h" 34 #include "irc_vbr_storage_vbv.h" 35 #include "irc_trace_support.h" 36 37 #define MAX(x, y) ((x) > (y) ? (x) : (y)) 38 39 typedef struct vbr_storage_vbv_t 40 { 41 WORD32 i4_max_buf_size; 42 WORD32 i4_cur_buf_size; 43 WORD32 i4_max_bits_inflow_per_frm_period; 44 WORD32 i4_max_bits_per_tgt_frm; 45 /* Storing input variables */ 46 WORD32 i4_max_bit_rate; 47 WORD32 i4_max_frame_rate; 48 /* Error bits calculation module */ 49 error_bits_handle ps_error_bits; 50 51 } vbr_storage_vbv_t; 52 53 static void overflow_avoided_summation(WORD32 *pi4_accumulator, WORD32 i4_input) 54 { 55 if((pi4_accumulator[0] > 0) 56 && (((int)0x7fffffff - pi4_accumulator[0]) < i4_input)) 57 { 58 pi4_accumulator[0] = 0x7fffffff; 59 } 60 else if((pi4_accumulator[0] < 0) 61 && (((int)0x80000000 - pi4_accumulator[0]) > i4_input)) 62 { 63 pi4_accumulator[0] = 0x80000000; 64 } 65 else 66 { 67 pi4_accumulator[0] += i4_input; 68 } 69 } 70 71 WORD32 irc_vbr_vbv_num_fill_use_free_memtab(vbr_storage_vbv_t **pps_vbr_storage_vbv, 72 itt_memtab_t *ps_memtab, 73 ITT_FUNC_TYPE_E e_func_type) 74 { 75 WORD32 i4_mem_tab_idx = 0; 76 vbr_storage_vbv_t s_vbr_storage_vbv_temp; 77 78 /* 79 * Hack for al alloc, during which we don't have any state memory. 80 * Dereferencing can cause issues 81 */ 82 if(e_func_type == GET_NUM_MEMTAB || e_func_type == FILL_MEMTAB) 83 (*pps_vbr_storage_vbv) = &s_vbr_storage_vbv_temp; 84 85 /*for src rate control state structure*/ 86 if(e_func_type != GET_NUM_MEMTAB) 87 { 88 fill_memtab(&ps_memtab[i4_mem_tab_idx], sizeof(vbr_storage_vbv_t), 89 ALIGN_128_BYTE, PERSISTENT, DDR); 90 use_or_fill_base(&ps_memtab[0], (void**)pps_vbr_storage_vbv, 91 e_func_type); 92 } 93 i4_mem_tab_idx++; 94 95 i4_mem_tab_idx += irc_error_bits_num_fill_use_free_memtab( 96 &pps_vbr_storage_vbv[0]->ps_error_bits, 97 &ps_memtab[i4_mem_tab_idx], e_func_type); 98 return (i4_mem_tab_idx); 99 } 100 101 void irc_init_vbr_vbv(vbr_storage_vbv_t *ps_vbr_storage_vbv, 102 WORD32 i4_max_bit_rate, 103 WORD32 i4_frm_rate, 104 WORD32 i4_max_vbv_buff_size) 105 { 106 ps_vbr_storage_vbv->i4_max_buf_size = i4_max_vbv_buff_size; 107 ps_vbr_storage_vbv->i4_cur_buf_size = i4_max_vbv_buff_size; 108 109 /* 110 * Calculate the max number of bits that flow into the decoder 111 * in the interval of two frames 112 */ 113 X_PROD_Y_DIV_Z(i4_max_bit_rate, 1000, i4_frm_rate, 114 ps_vbr_storage_vbv->i4_max_bits_inflow_per_frm_period); 115 116 /* init error bits */ 117 irc_init_error_bits(ps_vbr_storage_vbv->ps_error_bits, i4_frm_rate, 118 i4_max_bit_rate); 119 120 /* Storing the input values */ 121 ps_vbr_storage_vbv->i4_max_bits_per_tgt_frm = 122 ps_vbr_storage_vbv->i4_max_bits_inflow_per_frm_period; 123 ps_vbr_storage_vbv->i4_max_bit_rate = i4_max_bit_rate; 124 ps_vbr_storage_vbv->i4_max_frame_rate = i4_frm_rate; 125 } 126 127 void irc_update_vbr_vbv(vbr_storage_vbv_t *ps_vbr_storage_vbv, 128 WORD32 i4_total_bits_decoded) 129 { 130 WORD32 i4_error_bits = irc_get_error_bits( 131 ps_vbr_storage_vbv->ps_error_bits); 132 /* 133 * In the time interval between two decoded frames the buffer would have been 134 * filled up by the max_bits_inflow_per_frm_period. 135 */ 136 overflow_avoided_summation( 137 &ps_vbr_storage_vbv->i4_cur_buf_size, 138 (ps_vbr_storage_vbv->i4_max_bits_inflow_per_frm_period 139 + i4_error_bits)); 140 141 if(ps_vbr_storage_vbv->i4_cur_buf_size 142 > ps_vbr_storage_vbv->i4_max_buf_size) 143 { 144 ps_vbr_storage_vbv->i4_cur_buf_size = 145 ps_vbr_storage_vbv->i4_max_buf_size; 146 } 147 148 ps_vbr_storage_vbv->i4_cur_buf_size -= i4_total_bits_decoded; 149 150 /* Update the error bits state */ 151 irc_update_error_bits(ps_vbr_storage_vbv->ps_error_bits); 152 153 } 154 155 WORD32 irc_get_max_target_bits(vbr_storage_vbv_t *ps_vbr_storage_vbv) 156 { 157 WORD32 i4_cur_buf_size = ps_vbr_storage_vbv->i4_cur_buf_size; 158 WORD32 i4_error_bits = irc_get_error_bits( 159 ps_vbr_storage_vbv->ps_error_bits); 160 161 /* The buffer size when the next frame is decoded */ 162 overflow_avoided_summation( 163 &i4_cur_buf_size, 164 (ps_vbr_storage_vbv->i4_max_bits_inflow_per_frm_period 165 + i4_error_bits)); 166 if(i4_cur_buf_size > ps_vbr_storage_vbv->i4_max_buf_size) 167 { 168 i4_cur_buf_size = ps_vbr_storage_vbv->i4_max_buf_size; 169 } 170 171 /* 172 * Thus for the next frame the maximum number of bits the decoder can consume 173 * without underflow is i4_cur_buf_size 174 */ 175 return i4_cur_buf_size; 176 } 177 178 /**************************************************************************** 179 Function Name : irc_get_buffer_status 180 Description : Gets the state of VBV buffer 181 Inputs : Rate control API , header and texture bits 182 Outputs : 0 = normal, 1 = underflow, 2= overflow 183 Returns : vbv_buf_status_e 184 *****************************************************************************/ 185 vbv_buf_status_e irc_get_vbv_buffer_status(vbr_storage_vbv_t *ps_vbr_storage_vbv, 186 WORD32 i4_total_frame_bits, 187 WORD32 *pi4_num_bits_to_prevent_vbv_underflow) 188 { 189 vbv_buf_status_e e_buf_status; 190 WORD32 i4_cur_buf; 191 WORD32 i4_error_bits = irc_get_error_bits( 192 ps_vbr_storage_vbv->ps_error_bits); 193 194 /* error bits due to fixed point computation of drain rate*/ 195 i4_cur_buf = ps_vbr_storage_vbv->i4_cur_buf_size; 196 overflow_avoided_summation( 197 &i4_cur_buf, 198 (ps_vbr_storage_vbv->i4_max_bits_inflow_per_frm_period 199 + i4_error_bits)); 200 201 if(i4_cur_buf > ps_vbr_storage_vbv->i4_max_buf_size) 202 { 203 i4_cur_buf = ps_vbr_storage_vbv->i4_max_buf_size; 204 } 205 206 pi4_num_bits_to_prevent_vbv_underflow[0] = i4_cur_buf; 207 208 i4_cur_buf -= i4_total_frame_bits; 209 if(i4_cur_buf < 0) 210 { 211 e_buf_status = VBV_UNDERFLOW; 212 } 213 else if(i4_cur_buf > ps_vbr_storage_vbv->i4_max_buf_size) 214 { 215 e_buf_status = VBV_OVERFLOW; 216 } 217 else if(i4_cur_buf < (ps_vbr_storage_vbv->i4_max_buf_size >> 2)) 218 { 219 e_buf_status = VBR_CAUTION; 220 } 221 else 222 { 223 e_buf_status = VBV_NORMAL; 224 } 225 226 return e_buf_status; 227 } 228 229 UWORD8 irc_restrict_swing_dvd_comp(vbr_storage_vbv_t *ps_vbr_storage_vbv) 230 { 231 UWORD8 u1_restrict_swing = 1; 232 233 if(ps_vbr_storage_vbv->i4_cur_buf_size 234 < (ps_vbr_storage_vbv->i4_max_buf_size >> 1)) 235 { 236 u1_restrict_swing = 0; 237 } 238 239 return (u1_restrict_swing); 240 } 241 242 WORD32 irc_get_max_vbv_buf_size(vbr_storage_vbv_t *ps_vbr_storage_vbv) 243 { 244 return (ps_vbr_storage_vbv->i4_max_buf_size); 245 } 246 247 WORD32 irc_get_cur_vbv_buf_size(vbr_storage_vbv_t *ps_vbr_storage_vbv) 248 { 249 return (ps_vbr_storage_vbv->i4_cur_buf_size); 250 } 251 252 WORD32 irc_get_max_bits_inflow_per_frm_periode(vbr_storage_vbv_t *ps_vbr_storage_vbv) 253 { 254 return (ps_vbr_storage_vbv->i4_max_bits_inflow_per_frm_period); 255 } 256 257 WORD32 irc_get_max_bits_per_tgt_frm(vbr_storage_vbv_t *ps_vbr_storage_vbv) 258 { 259 return (ps_vbr_storage_vbv->i4_max_bits_per_tgt_frm); 260 } 261 262 WORD32 irc_vbv_get_vbv_buf_fullness(vbr_storage_vbv_t *ps_vbr_storage_vbv, 263 UWORD32 u4_bits) 264 { 265 WORD32 i4_error_bits = irc_get_error_bits( 266 ps_vbr_storage_vbv->ps_error_bits); 267 WORD32 i4_cur_buf_size = ps_vbr_storage_vbv->i4_cur_buf_size; 268 269 overflow_avoided_summation( 270 &i4_cur_buf_size, 271 (ps_vbr_storage_vbv->i4_max_bits_inflow_per_frm_period 272 + i4_error_bits)); 273 274 if(i4_cur_buf_size > ps_vbr_storage_vbv->i4_max_buf_size) 275 { 276 i4_cur_buf_size = ps_vbr_storage_vbv->i4_max_buf_size; 277 } 278 279 i4_cur_buf_size -= u4_bits; 280 281 return (i4_cur_buf_size); 282 } 283 284 WORD32 irc_get_max_tgt_bits_dvd_comp(vbr_storage_vbv_t *ps_vbr_storage_vbv, 285 WORD32 i4_rem_bits_in_gop, 286 WORD32 i4_rem_frms_in_gop, 287 picture_type_e e_pic_type) 288 { 289 WORD32 i4_dbf_max, i4_dbf_min, i4_dbf_prev, i4_vbv_size, i4_dbf_desired; 290 WORD32 i4_max_tgt_bits; 291 292 i4_vbv_size = ps_vbr_storage_vbv->i4_max_buf_size; 293 i4_dbf_max = 95 * i4_vbv_size / 100; 294 i4_dbf_min = 10 * i4_vbv_size / 100; 295 i4_dbf_prev = ps_vbr_storage_vbv->i4_cur_buf_size; 296 297 if(i4_rem_bits_in_gop < 0) 298 i4_rem_bits_in_gop = 0; 299 if(i4_rem_frms_in_gop <= 0) 300 i4_rem_frms_in_gop = 1; 301 302 if(e_pic_type == I_PIC) 303 { 304 i4_dbf_desired = i4_dbf_min; 305 } 306 else 307 { 308 i4_dbf_desired = (i4_dbf_max - i4_rem_bits_in_gop / i4_rem_frms_in_gop 309 - i4_dbf_prev) / i4_rem_frms_in_gop; 310 i4_dbf_desired += i4_dbf_prev; 311 } 312 313 i4_dbf_prev += ps_vbr_storage_vbv->i4_max_bits_inflow_per_frm_period; 314 if(i4_dbf_prev > ps_vbr_storage_vbv->i4_max_buf_size) 315 { 316 i4_dbf_prev = ps_vbr_storage_vbv->i4_max_buf_size; 317 } 318 319 i4_max_tgt_bits = MAX(0, (i4_dbf_prev - i4_dbf_desired)); 320 return (i4_max_tgt_bits); 321 } 322 323 void irc_change_vbr_vbv_frame_rate(vbr_storage_vbv_t *ps_vbr_storage_vbv, 324 WORD32 i4_frm_rate) 325 { 326 /* 327 * Calculate the max number of bits that flow into the decoder 328 * in the interval of two frames 329 */ 330 X_PROD_Y_DIV_Z(ps_vbr_storage_vbv->i4_max_bit_rate, 1000, i4_frm_rate, 331 ps_vbr_storage_vbv->i4_max_bits_inflow_per_frm_period); 332 333 /* Update the lower modules */ 334 irc_change_frm_rate_in_error_bits(ps_vbr_storage_vbv->ps_error_bits, 335 i4_frm_rate); 336 /* Storing the input values */ 337 ps_vbr_storage_vbv->i4_max_frame_rate = i4_frm_rate; 338 } 339 340 void irc_change_vbr_vbv_bit_rate(vbr_storage_vbv_t *ps_vbr_storage_vbv, 341 WORD32 i4_max_bit_rate) 342 { 343 /* 344 * Calculate the max number of bits that flow into the decoder 345 * in the interval of two frames 346 */ 347 X_PROD_Y_DIV_Z(i4_max_bit_rate, 1000, ps_vbr_storage_vbv->i4_max_frame_rate, 348 ps_vbr_storage_vbv->i4_max_bits_inflow_per_frm_period); 349 350 /* update the lower modules */ 351 irc_change_bitrate_in_error_bits(ps_vbr_storage_vbv->ps_error_bits, 352 i4_max_bit_rate); 353 354 /* Storing the input values */ 355 ps_vbr_storage_vbv->i4_max_bit_rate = i4_max_bit_rate; 356 } 357 358 void irc_change_vbr_max_bits_per_tgt_frm(vbr_storage_vbv_t *ps_vbr_storage_vbv, 359 WORD32 i4_tgt_frm_rate) 360 { 361 /* 362 * Calculate the max number of bits that flow into the decoder 363 * in the interval of two frames 364 */ 365 X_PROD_Y_DIV_Z(ps_vbr_storage_vbv->i4_max_bit_rate, 1000, i4_tgt_frm_rate, 366 ps_vbr_storage_vbv->i4_max_bits_per_tgt_frm); 367 368 } 369
