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      1 /* TI C6X opcode information.
      2    Copyright (C) 2010-2014 Free Software Foundation, Inc.
      3 
      4    This program is free software; you can redistribute it and/or modify
      5    it under the terms of the GNU General Public License as published by
      6    the Free Software Foundation; either version 3 of the License, or
      7    (at your option) any later version.
      8 
      9    This program is distributed in the hope that it will be useful,
     10    but WITHOUT ANY WARRANTY; without even the implied warranty of
     11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     12    GNU General Public License for more details.
     13 
     14    You should have received a copy of the GNU General Public License
     15    along with this program; if not, write to the Free Software
     16    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
     17    MA 02110-1301, USA.  */
     18 
     19 #ifndef OPCODE_TIC6X_H
     20 #define OPCODE_TIC6X_H
     21 
     22 #include "bfd.h"
     23 #include "symcat.h"
     24 
     25 /* A field in an instruction format.  The names are based on those
     26    used in the architecture manuals.  */
     27 typedef enum
     28   {
     29     tic6x_field_baseR,
     30     tic6x_field_cc,
     31     tic6x_field_creg,
     32     tic6x_field_cst,
     33     tic6x_field_csta,
     34     tic6x_field_cstb,
     35     tic6x_field_dst,
     36     tic6x_field_dstms,
     37     tic6x_field_dw,
     38     tic6x_field_fstgfcyc,
     39     tic6x_field_h,
     40     tic6x_field_ii,
     41     tic6x_field_mask,
     42     tic6x_field_mode,
     43     tic6x_field_n,
     44     tic6x_field_na,
     45     tic6x_field_offsetR,
     46     tic6x_field_op,
     47     tic6x_field_p,
     48     tic6x_field_ptr,
     49     tic6x_field_r,
     50     tic6x_field_s,
     51     tic6x_field_sc,
     52     tic6x_field_src,
     53     tic6x_field_src1,
     54     tic6x_field_src2,
     55     tic6x_field_srcdst,
     56     tic6x_field_srcms,
     57     tic6x_field_sn,
     58     tic6x_field_sz,
     59     tic6x_field_unit,
     60     tic6x_field_t,
     61     tic6x_field_x,
     62     tic6x_field_y,
     63     tic6x_field_z
     64   } tic6x_insn_field_id;
     65 
     66 typedef struct
     67 {
     68   /* The least-significant bit position in the field.  */
     69   unsigned short low_pos;
     70 
     71   /* The number of bits in the field.  */
     72   unsigned short width;
     73   /* The position of the bitfield in the field. */
     74   unsigned short pos;
     75 } tic6x_bitfield;
     76 
     77 /* Maximum number of subfields in composite field.  */
     78 #define TIC6X_MAX_BITFIELDS 4
     79 
     80 typedef struct
     81 {
     82   /* The name used to reference the field.  */
     83   tic6x_insn_field_id field_id;
     84   unsigned int num_bitfields;
     85   tic6x_bitfield bitfields[TIC6X_MAX_BITFIELDS];
     86 } tic6x_insn_field;
     87 
     88 /* Maximum number of variable fields in an instruction format.  */
     89 #define TIC6X_MAX_INSN_FIELDS 11
     90 
     91 /* A particular instruction format.  */
     92 typedef struct
     93 {
     94   /* How many bits in the instruction.  */
     95   unsigned int num_bits;
     96 
     97   /* Constant bits in the instruction.  */
     98   unsigned int cst_bits;
     99 
    100   /* Mask matching those bits.  */
    101   unsigned int mask;
    102 
    103   /* The number of instruction fields.  */
    104   unsigned int num_fields;
    105 
    106   /* Descriptions of instruction fields.  */
    107   tic6x_insn_field fields[TIC6X_MAX_INSN_FIELDS];
    108 } tic6x_insn_format;
    109 
    110 /* An index into the table of instruction formats.  */
    111 typedef enum
    112   {
    113 #define FMT(name, num_bits, cst_bits, mask, fields)	\
    114   CONCAT2(tic6x_insn_format_, name),
    115 #include "tic6x-insn-formats.h"
    116 #undef FMT
    117     tic6x_insn_format_max
    118   } tic6x_insn_format_id;
    119 
    120 /* The table itself.  */
    121 extern const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max];
    122 
    123 /* If instruction format FMT has a field FIELD, return a pointer to
    124    the description of that field; otherwise return NULL.  */
    125 
    126 const tic6x_insn_field *tic6x_field_from_fmt (const tic6x_insn_format *fmt,
    127 					      tic6x_insn_field_id field);
    128 
    129 /* Description of a field (in an instruction format) whose value is
    130    fixed, or constrained to be in a particular range, in a particular
    131    opcode.  */
    132 typedef struct
    133 {
    134   /* The name of the field.  */
    135   tic6x_insn_field_id field_id;
    136 
    137   /* The least value of the field in this instruction.  */
    138   unsigned int min_val;
    139 
    140   /* The greatest value of the field in this instruction.  */
    141   unsigned int max_val;
    142 } tic6x_fixed_field;
    143 
    144 /* Pseudo opcode fields position for compact instructions
    145    If 16 bits instruction detected, the opcode is enriched
    146    [DSZ/3][BR][SAT][opcode] */
    147 #define TIC6X_COMPACT_SAT_POS 16
    148 #define TIC6X_COMPACT_BR_POS 17
    149 #define TIC6X_COMPACT_DSZ_POS 18
    150 
    151 /* Bit-masks for defining instructions present on some subset of
    152    processors; each indicates an instruction present on that processor
    153    and those that are supersets of it.  The options passed to the
    154    assembler determine a bit-mask ANDed with the bit-mask indicating
    155    when the instruction was added to determine whether the instruction
    156    is enabled.  */
    157 #define TIC6X_INSN_C62X		0x0001
    158 #define TIC6X_INSN_C64X		0x0002
    159 #define TIC6X_INSN_C64XP	0x0004
    160 #define TIC6X_INSN_C67X		0x0008
    161 #define TIC6X_INSN_C67XP	0x0010
    162 #define TIC6X_INSN_C674X	0x0020
    163 
    164 /* Flags with further information about an opcode table entry.  */
    165 
    166 /* Only used by the assembler, not the disassembler.  */
    167 #define TIC6X_FLAG_MACRO	0x0001
    168 
    169 /* Must be first in its execute packet.  */
    170 #define TIC6X_FLAG_FIRST	0x0002
    171 
    172 /* Multi-cycle NOP (not used for the NOP n instruction itself, which
    173    is only a multicycle NOP if n > 1).  */
    174 #define TIC6X_FLAG_MCNOP	0x0004
    175 
    176 /* Cannot be in parallel with a multi-cycle NOP.  */
    177 #define TIC6X_FLAG_NO_MCNOP	0x0008
    178 
    179 /* Load instruction.  */
    180 #define TIC6X_FLAG_LOAD		0x0010
    181 
    182 /* Store instruction.  */
    183 #define TIC6X_FLAG_STORE	0x0020
    184 
    185 /* Unaligned memory operation.  */
    186 #define TIC6X_FLAG_UNALIGNED	0x0040
    187 
    188 /* Only on side B.  */
    189 #define TIC6X_FLAG_SIDE_B_ONLY	0x0080
    190 
    191 /* Only on data path T2.  */
    192 #define TIC6X_FLAG_SIDE_T2_ONLY	0x0100
    193 
    194 /* Does not support cross paths.  */
    195 #define TIC6X_FLAG_NO_CROSS	0x0200
    196 
    197 /* Annotate this branch instruction as a call.  */
    198 #define TIC6X_FLAG_CALL		0x0400
    199 
    200 /* Annotate this branch instruction as a return.  */
    201 #define TIC6X_FLAG_RETURN	0x0800
    202 
    203 /* This instruction starts a software pipelined loop.  */
    204 #define TIC6X_FLAG_SPLOOP	0x1000
    205 
    206 /* This instruction ends a software pipelined loop.  */
    207 #define TIC6X_FLAG_SPKERNEL	0x2000
    208 
    209 /* This instruction takes a list of functional units as parameters;
    210    although described as having one parameter, the number may be 0 to
    211    8.  */
    212 #define TIC6X_FLAG_SPMASK	0x4000
    213 
    214 /* When more than one opcode matches the assembly source, prefer the
    215    one with the highest value for this bit-field.  If two opcode table
    216    entries can match the same syntactic form, they must have different
    217    values here.  */
    218 #define TIC6X_PREFER_VAL(n)	(((n) & 0x8000) >> 15)
    219 #define TIC6X_FLAG_PREFER(n)	((n) << 15)
    220 
    221 /* 16 bits opcode is predicated by register a0 (s = 0) or b0 (s = 1) */
    222 #define TIC6X_FLAG_INSN16_SPRED      0x00100000
    223 /* 16 bits opcode ignores RS bit of fetch packet header */
    224 #define TIC6X_FLAG_INSN16_NORS       0x00200000
    225 /* 16 bits opcode only on side B */
    226 #define TIC6X_FLAG_INSN16_BSIDE      0x00400000
    227 /* 16 bits opcode ptr reg is b15 */
    228 #define TIC6X_FLAG_INSN16_B15PTR     0x00800000
    229 /* 16 bits opcode memory access modes */
    230 #define TIC6X_INSN16_MEM_MODE(n)           ((n) << 16)
    231 #define TIC6X_INSN16_MEM_MODE_VAL(n) (((n) & 0x000F0000) >> 16)
    232 #define TIC6X_MEM_MODE_NEGATIVE      0
    233 #define TIC6X_MEM_MODE_POSITIVE      1
    234 #define TIC6X_MEM_MODE_REG_NEGATIVE  4
    235 #define TIC6X_MEM_MODE_REG_POSITIVE  5
    236 #define TIC6X_MEM_MODE_PREDECR       8
    237 #define TIC6X_MEM_MODE_PREINCR       9
    238 #define TIC6X_MEM_MODE_POSTDECR      10
    239 #define TIC6X_MEM_MODE_POSTINCR      11
    240 
    241 #define TIC6X_FLAG_INSN16_MEM_MODE(mode) TIC6X_INSN16_MEM_MODE(TIC6X_MEM_MODE_##mode)
    242 
    243 #define TIC6X_NUM_PREFER	2
    244 
    245 /* Maximum number of fixed fields for a particular opcode.  */
    246 #define TIC6X_MAX_FIXED_FIELDS 4
    247 
    248 /* Maximum number of operands in the opcode table for a particular
    249    opcode.  */
    250 #define TIC6X_MAX_OPERANDS 4
    251 
    252 /* Maximum number of operands in the source code for a particular
    253    opcode (different from the number in the opcode table for SPMASK
    254    and SPMASKR).  */
    255 #define TIC6X_MAX_SOURCE_OPERANDS 8
    256 
    257 /* Maximum number of variable fields for a particular opcode.  */
    258 #define TIC6X_MAX_VAR_FIELDS 7
    259 
    260 /* Which functional units an opcode uses.  This only describes the
    261    basic choice of D, L, M, S or no functional unit; other fields are
    262    used to describe further restrictions (instructions only operating
    263    on one side), use of cross paths and load/store instructions using
    264    one side for the address and the other side for the source or
    265    destination register.  */
    266 typedef enum
    267   {
    268     tic6x_func_unit_d,
    269     tic6x_func_unit_l,
    270     tic6x_func_unit_m,
    271     tic6x_func_unit_s,
    272     tic6x_func_unit_nfu
    273   } tic6x_func_unit_base;
    274 
    275 /* Possible forms of source operand.  */
    276 typedef enum
    277   {
    278     /* An assembly-time constant.  */
    279     tic6x_operand_asm_const,
    280     /* A link-time constant.  */
    281     tic6x_operand_link_const,
    282     /* A register, from the same side as the functional unit
    283        selected.  */
    284     tic6x_operand_reg,
    285     /* A register, from the same side as the functional unit
    286        selected that ignore RS header bit */
    287     tic6x_operand_reg_nors,
    288     /* A register, from the b side */
    289     tic6x_operand_reg_bside,
    290     /* A register, from the b side and from the low register set */
    291     tic6x_operand_reg_bside_nors,
    292     /* A register, that is from the other side if a cross path is
    293        used.  */
    294     tic6x_operand_xreg,
    295     /* A register, that is from the side of the data path
    296        selected.  */
    297     tic6x_operand_dreg,
    298     /* An address register usable with 15-bit offsets (B14 or B15).
    299        This is from the same side as the functional unit if a cross
    300        path is not used, and the other side if a cross path is
    301        used.  */
    302     tic6x_operand_areg,
    303     /* The B15 register */
    304     tic6x_operand_b15reg,
    305     /* A register coded as an offset from either A16 or B16 depending
    306        on the value of the t bit. */
    307     tic6x_operand_treg,
    308     /* A register (A0 or B0), from the same side as the
    309        functional unit selected.  */
    310     tic6x_operand_zreg,
    311     /* A return address register (A3 or B3), from the same side as the
    312        functional unit selected.  */
    313     tic6x_operand_retreg,
    314     /* A register pair, from the same side as the functional unit
    315        selected.  */
    316     tic6x_operand_regpair,
    317     /* A register pair, that is from the other side if a cross path is
    318        used.  */
    319     tic6x_operand_xregpair,
    320     /* A register pair, from the side of the data path selected.  */
    321     tic6x_operand_dregpair,
    322     /* A register pair coded as an offset from either A16 or B16 depending
    323        on the value of the t bit. */
    324     tic6x_operand_tregpair,
    325     /* The literal string "irp" (case-insensitive).  */
    326     tic6x_operand_irp,
    327     /* The literal string "nrp" (case-insensitive).  */
    328     tic6x_operand_nrp,
    329     /* The literal string "ilc" (case-insensitive).  */
    330 	tic6x_operand_ilc,
    331     /* A control register.  */
    332     tic6x_operand_ctrl,
    333     /* A memory reference (base and offset registers from the side of
    334        the functional unit selected), using either unsigned 5-bit
    335        constant or register offset, if any offset; register offsets
    336        cannot use unscaled () syntax.  */
    337     tic6x_operand_mem_short,
    338     /* A memory reference (base and offset registers from the side of
    339        the functional unit selected), using either unsigned 5-bit
    340        constant or register offset, if any offset; register offsets
    341        can use unscaled () syntax (for LDNDW and STNDW).  */
    342     tic6x_operand_mem_ndw,
    343     /* A memory reference using 15-bit link-time constant offset
    344        relative to B14 or B15.  */
    345     tic6x_operand_mem_long,
    346     /* A memory reference that only dereferences a register with no
    347        further adjustments (*REG), that register being from the side
    348        of the functional unit selected.  */
    349     tic6x_operand_mem_deref,
    350     /* A functional unit name or a list thereof (for SPMASK and
    351        SPMASKR).  */
    352     tic6x_operand_func_unit,
    353     /* Hardwired constant '5' in Sbu8 Scs10 and Sbu8c 16 bits
    354        instruction formats - spru732j.pdf Appendix F.4 */
    355     tic6x_operand_hw_const_minus_1,
    356     tic6x_operand_hw_const_0,
    357     tic6x_operand_hw_const_1,
    358     tic6x_operand_hw_const_5,
    359     tic6x_operand_hw_const_16,
    360     tic6x_operand_hw_const_24,
    361     tic6x_operand_hw_const_31
    362   } tic6x_operand_form;
    363 
    364 /* Whether something is, or can be, read or written.  */
    365 typedef enum
    366   {
    367     tic6x_rw_none,
    368     tic6x_rw_read,
    369     tic6x_rw_write,
    370     tic6x_rw_read_write
    371   } tic6x_rw;
    372 
    373 /* Description of a source operand and how it is used.  */
    374 typedef struct
    375 {
    376   /* The syntactic form of the operand.  */
    377   tic6x_operand_form form;
    378 
    379   /* For non-constant operands, the size in bytes (1, 2, 4, 5 or
    380      8).  Ignored for constant operands.  */
    381   unsigned int size;
    382 
    383   /* Whether the operand is read, written or both.  In addition to the
    384      operations described here, address registers are read on cycle 1
    385      regardless of when the memory operand is read or written, and may
    386      be modified as described by the addressing mode, and control
    387      registers may be implicitly read by some instructions.  There are
    388      also some special cases not fully described by this
    389      structure.
    390 
    391      - For mpydp, the low part of src2 is read on cycles 1 and 3 but
    392        not 2, and the high part on cycles 2 and 4 but not 3.
    393 
    394      - The swap2 pseudo-operation maps to packlh2, reading the first
    395        operand of swap2 twice.  */
    396   tic6x_rw rw;
    397 
    398   /* The first and last cycles (1 for E1, etc.) at which the operand,
    399      or the low part for two-register operands, is read or
    400      written.  */
    401   unsigned short low_first;
    402   unsigned short low_last;
    403 
    404   /* Likewise, for the high part.  */
    405   unsigned short high_first;
    406   unsigned short high_last;
    407 } tic6x_operand_info;
    408 
    409 /* Ways of converting an operand or functional unit specifier to a
    410    field value.  */
    411 typedef enum
    412   {
    413     /* Store an unsigned assembly-time constant (which must fit) in
    414        the field.  */
    415     tic6x_coding_ucst,
    416     /* Store a signed constant (which must fit) in the field.  This
    417        may be used both for assembly-time constants and for link-time
    418        constants.  */
    419     tic6x_coding_scst,
    420     /* Subtract one from an unsigned assembly-time constant (which
    421        must be strictly positive before the subtraction) and store the
    422        value (which must fit) in the field.  */
    423     tic6x_coding_ucst_minus_one,
    424     /* Negate a signed assembly-time constant, and store the result of
    425        negation (which must fit) in the field.  Used only for
    426        pseudo-operations.  */
    427     tic6x_coding_scst_negate,
    428     /* Store an unsigned link-time constant, implicitly DP-relative
    429        and counting in bytes, in the field.  For expression operands,
    430        assembly-time constants are encoded as-is.  For memory
    431        reference operands, the offset is encoded as-is if [] syntax is
    432        used and shifted if () is used.  */
    433     tic6x_coding_ulcst_dpr_byte,
    434     /* Store an unsigned link-time constant, implicitly DP-relative
    435        and counting in half-words, in the field.  For expression
    436        operands, assembly-time constants are encoded as-is.  For
    437        memory reference operands, the offset is encoded as-is if []
    438        syntax is used and shifted if () is used.  */
    439     tic6x_coding_ulcst_dpr_half,
    440     /* Store an unsigned link-time constant, implicitly DP-relative
    441        and counting in words, in the field.  For expression operands,
    442        assembly-time constants are encoded as-is.  For memory
    443        reference operands, the offset is encoded as-is if [] syntax is
    444        used and shifted if () is used.  */
    445     tic6x_coding_ulcst_dpr_word,
    446     /* Store the low 16 bits of a link-time constant in the field;
    447        considered unsigned for disassembly.  */
    448     tic6x_coding_lcst_low16,
    449     /* Store the high 16 bits of a link-time constant in the field;
    450        considered unsigned for disassembly.  */
    451     tic6x_coding_lcst_high16,
    452     /* Store a signed PC-relative value (address of label minus
    453        address of fetch packet containing the current instruction,
    454        counted in words) in the field.  */
    455     tic6x_coding_pcrel,
    456     /* Likewise, but counting in half-words if in a header-based fetch
    457        packet.  */
    458     tic6x_coding_pcrel_half,
    459     /* Store an unsigned PC-relative value used in compact insn */
    460     tic6x_coding_pcrel_half_unsigned,
    461     /* Encode the register number (even number for a register pair) in
    462        the field.  When applied to a memory reference, encode the base
    463        register.  */
    464     tic6x_coding_reg,
    465     /* Encode the register-pair's lsb (even register) for instructions
    466        that use src1 as port for loading lsb of double-precision
    467        operand value (absdp, dpint, dpsp, dptrunc, rcpdp, rsqrdp).  */
    468     tic6x_coding_regpair_lsb,
    469     /* Encode the register-pair's msb (odd register), see above.  */
    470     tic6x_coding_regpair_msb,
    471     /* Store 0 for register B14, 1 for register B15.  When applied to
    472        a memory reference, encode the base register.  */
    473     tic6x_coding_areg,
    474     /* Compact instruction offset base register */
    475     tic6x_coding_reg_ptr,
    476     /* Store the low part of a control register address.  */
    477     tic6x_coding_crlo,
    478     /* Store the high part of a control register address.  */
    479     tic6x_coding_crhi,
    480     /* Encode the even register number for a register pair, shifted
    481        right by one bit.  */
    482     tic6x_coding_reg_shift,
    483     /* Store either the offset register or the 5-bit unsigned offset
    484        for a memory reference.  If an offset uses the unscaled ()
    485        form, which is only permitted with constants, it is scaled
    486        according to the access size of the operand before being
    487        stored.  */
    488     tic6x_coding_mem_offset,
    489     /* Store either the offset register or the 5-bit unsigned offset
    490        for a memory reference, but with no scaling applied to the
    491        offset (for nonaligned doubleword operations).  */
    492     tic6x_coding_mem_offset_noscale,
    493     /* Store the addressing mode for a memory reference.  */
    494     tic6x_coding_mem_mode,
    495     /* Store whether a memory reference is scaled.  */
    496     tic6x_coding_scaled,
    497     /* Store the stage in an SPKERNEL instruction in the upper part of
    498        the field.  */
    499     tic6x_coding_fstg,
    500     /* Store the cycle in an SPKERNEL instruction in the lower part of
    501        the field.  */
    502     tic6x_coding_fcyc,
    503     /* Store the mask bits for functional units in the field in an
    504        SPMASK or SPMASKR instruction.  */
    505     tic6x_coding_spmask,
    506     /* Store the number of a register that is unused, or minimally
    507        used, in this execute packet.  The number must be the same for
    508        all uses of this coding in a single instruction, but may be
    509        different for different instructions in the execute packet.
    510        This is for the "zero" pseudo-operation.  This is not safe when
    511        reads may occur from instructions in previous execute packets;
    512        in such cases the programmer or compiler should use explicit
    513        "sub" instructions for those cases of "zero" that cannot be
    514        implemented as "mvk" for the processor specified.  */
    515     tic6x_coding_reg_unused,
    516     /* Store 1 if the functional unit used is on side B, 0 for side
    517        A.  */
    518     tic6x_coding_fu,
    519     /* Store 1 if the data path used (source register for store,
    520        destination for load) is on side B, 0 for side A.  */
    521     tic6x_coding_data_fu,
    522     /* Store 1 if the cross path is being used, 0 otherwise.  */
    523     tic6x_coding_xpath,
    524     /* L3i constant coding */
    525     tic6x_coding_scst_l3i,
    526     /* S3i constant coding */
    527     tic6x_coding_cst_s3i,
    528     /* mem offset minus 1 */
    529     tic6x_coding_mem_offset_minus_one,
    530     /* non aligned mem offset minus 1 */
    531     tic6x_coding_mem_offset_minus_one_noscale,
    532     tic6x_coding_rside
    533   } tic6x_coding_method;
    534 
    535 /* How to generate the value of a particular field.  */
    536 typedef struct
    537 {
    538   /* The name of the field.  */
    539   tic6x_insn_field_id field_id;
    540 
    541   /* How it is encoded.  */
    542   tic6x_coding_method coding_method;
    543 
    544   /* Source operand number, if any.  */
    545   unsigned int operand_num;
    546 } tic6x_coding_field;
    547 
    548 /* Types of instruction for pipeline purposes.  The type determines
    549    functional unit and cross path latency (when the same functional
    550    unit can be used by other instructions, when the same cross path
    551    can be used by other instructions).  */
    552 typedef enum
    553   {
    554     tic6x_pipeline_nop,
    555     tic6x_pipeline_1cycle,
    556     tic6x_pipeline_1616_m,
    557     tic6x_pipeline_store,
    558     tic6x_pipeline_mul_ext,
    559     tic6x_pipeline_load,
    560     tic6x_pipeline_branch,
    561     tic6x_pipeline_2cycle_dp,
    562     tic6x_pipeline_4cycle,
    563     tic6x_pipeline_intdp,
    564     tic6x_pipeline_dpcmp,
    565     tic6x_pipeline_addsubdp,
    566     tic6x_pipeline_mpyi,
    567     tic6x_pipeline_mpyid,
    568     tic6x_pipeline_mpydp,
    569     tic6x_pipeline_mpyspdp,
    570     tic6x_pipeline_mpysp2dp
    571   } tic6x_pipeline_type;
    572 
    573 /* Description of a control register.  */
    574 typedef struct
    575 {
    576   /* The name of the register.  */
    577   const char *name;
    578 
    579   /* Which ISA variants include this control register.  */
    580   unsigned short isa_variants;
    581 
    582   /* Whether it can be read, written or both (in supervisor mode).
    583      Some registers use the same address, but different names, for
    584      reading and writing.  */
    585   tic6x_rw rw;
    586 
    587   /* crlo value for this register.  */
    588   unsigned int crlo;
    589 
    590   /* Mask that, ANDed with the crhi value in the instruction, must be
    591      0.  0 is always generated when generating code.  */
    592   unsigned int crhi_mask;
    593 } tic6x_ctrl;
    594 
    595 /* An index into the table of control registers.  */
    596 typedef enum
    597   {
    598 #define CTRL(name, isa, rw, crlo, crhi_mask)	\
    599     CONCAT2(tic6x_ctrl_,name),
    600 #include "tic6x-control-registers.h"
    601 #undef CTRL
    602     tic6x_ctrl_max
    603   } tic6x_ctrl_id;
    604 
    605 /* The table itself.  */
    606 extern const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max];
    607 
    608 /* An entry in the opcode table.  */
    609 typedef struct
    610 {
    611   /* The name of the instruction.  */
    612   const char *name;
    613 
    614   /* Functional unit used by this instruction (basic information).  */
    615   tic6x_func_unit_base func_unit;
    616 
    617   /* The format of this instruction.  */
    618   tic6x_insn_format_id format;
    619 
    620   /* The pipeline type of this instruction.  */
    621   tic6x_pipeline_type type;
    622 
    623   /* Which ISA variants include this instruction.  */
    624   unsigned short isa_variants;
    625 
    626   /* Flags for this instruction.  */
    627   unsigned int flags;
    628 
    629   /* Number of fixed fields, or fields with restricted value ranges,
    630      for this instruction.  */
    631   unsigned int num_fixed_fields;
    632 
    633   /* Values of fields fixed for this instruction.  */
    634   tic6x_fixed_field fixed_fields[TIC6X_MAX_FIXED_FIELDS];
    635 
    636   /* The number of operands in the source form of this
    637      instruction.  */
    638   unsigned int num_operands;
    639 
    640   /* Information about individual operands.  */
    641   tic6x_operand_info operand_info[TIC6X_MAX_OPERANDS];
    642 
    643   /* The number of variable fields for this instruction with encoding
    644      instructions explicitly given.  */
    645   unsigned int num_variable_fields;
    646 
    647   /* How fields (other than ones with fixed value) are computed from
    648      the source operands and functional unit specifiers.  In addition
    649      to fields specified here:
    650 
    651      - creg, if present, is set from the predicate, along with z which
    652        must be present if creg is present.
    653 
    654      - p, if present (on all non-compact instructions), is set from
    655        the parallel bars.
    656   */
    657   tic6x_coding_field variable_fields[TIC6X_MAX_VAR_FIELDS];
    658 } tic6x_opcode;
    659 
    660 /* An index into the table of opcodes.  */
    661 typedef enum
    662   {
    663 #define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \
    664     CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
    665 #define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
    666     CONCAT4(tic6x_opcode_,name,_,e),
    667 #define INSNU(name, func_unit, format, type, isa, flags, fixed, ops, var) \
    668     CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
    669 #define INSNUE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
    670     CONCAT6(tic6x_opcode_,name,_,func_unit,_,e),
    671 #include "tic6x-opcode-table.h"
    672 #undef INSN
    673 #undef INSNE
    674 #undef INSNU
    675 #undef INSNUE
    676     tic6x_opcode_max
    677   } tic6x_opcode_id;
    678 
    679 /* The table itself.  */
    680 extern const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max];
    681 
    682 /* A linked list of opcodes.  */
    683 typedef struct tic6x_opcode_list_tag
    684 {
    685   tic6x_opcode_id id;
    686   struct tic6x_opcode_list_tag *next;
    687 } tic6x_opcode_list;
    688 
    689 /* The information from a fetch packet header.  */
    690 typedef struct
    691 {
    692   /* The header itself.  */
    693   unsigned int header;
    694 
    695   /* Whether each word uses compact instructions.  */
    696   bfd_boolean word_compact[7];
    697 
    698   /* Whether loads are protected.  */
    699   bfd_boolean prot;
    700 
    701   /* Whether instructions use the high register set.  */
    702   bfd_boolean rs;
    703 
    704   /* Data size.  */
    705   unsigned int dsz;
    706 
    707   /* Whether compact instructions in the S unit are decoded as
    708      branches.  */
    709   bfd_boolean br;
    710 
    711   /* Whether compact instructions saturate.  */
    712   bfd_boolean sat;
    713 
    714   /* P-bits.  */
    715   bfd_boolean p_bits[14];
    716 } tic6x_fetch_packet_header;
    717 
    718 #endif /* OPCODE_TIC6X_H */
    719