1 /* Assemble Matsushita MN10200 instructions. 2 Copyright (C) 1996-2014 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 #include "sysdep.h" 22 #include "opcode/mn10200.h" 23 24 25 const struct mn10200_operand mn10200_operands[] = { 27 #define UNUSED 0 28 {0, 0, 0}, 29 30 /* dn register in the first register operand position. */ 31 #define DN0 (UNUSED+1) 32 {2, 0, MN10200_OPERAND_DREG}, 33 34 /* dn register in the second register operand position. */ 35 #define DN1 (DN0+1) 36 {2, 2, MN10200_OPERAND_DREG}, 37 38 /* dm register in the first register operand position. */ 39 #define DM0 (DN1+1) 40 {2, 0, MN10200_OPERAND_DREG}, 41 42 /* dm register in the second register operand position. */ 43 #define DM1 (DM0+1) 44 {2, 2, MN10200_OPERAND_DREG}, 45 46 /* an register in the first register operand position. */ 47 #define AN0 (DM1+1) 48 {2, 0, MN10200_OPERAND_AREG}, 49 50 /* an register in the second register operand position. */ 51 #define AN1 (AN0+1) 52 {2, 2, MN10200_OPERAND_AREG}, 53 54 /* am register in the first register operand position. */ 55 #define AM0 (AN1+1) 56 {2, 0, MN10200_OPERAND_AREG}, 57 58 /* am register in the second register operand position. */ 59 #define AM1 (AM0+1) 60 {2, 2, MN10200_OPERAND_AREG}, 61 62 /* 8 bit unsigned immediate which may promote to a 16bit 63 unsigned immediate. */ 64 #define IMM8 (AM1+1) 65 {8, 0, MN10200_OPERAND_PROMOTE}, 66 67 /* 16 bit unsigned immediate which may promote to a 32bit 68 unsigned immediate. */ 69 #define IMM16 (IMM8+1) 70 {16, 0, MN10200_OPERAND_PROMOTE}, 71 72 /* 16 bit pc-relative immediate which may promote to a 16bit 73 pc-relative immediate. */ 74 #define IMM16_PCREL (IMM16+1) 75 {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED}, 76 77 /* 16bit unsigned dispacement in a memory operation which 78 may promote to a 32bit displacement. */ 79 #define IMM16_MEM (IMM16_PCREL+1) 80 {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR}, 81 82 /* 24 immediate, low 16 bits in the main instruction 83 word, 8 in the extension word. */ 84 85 #define IMM24 (IMM16_MEM+1) 86 {24, 0, MN10200_OPERAND_EXTENDED}, 87 88 /* 32bit pc-relative offset. */ 89 #define IMM24_PCREL (IMM24+1) 90 {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED}, 91 92 /* 32bit memory offset. */ 93 #define IMM24_MEM (IMM24_PCREL+1) 94 {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR}, 95 96 /* Processor status word. */ 97 #define PSW (IMM24_MEM+1) 98 {0, 0, MN10200_OPERAND_PSW}, 99 100 /* MDR register. */ 101 #define MDR (PSW+1) 102 {0, 0, MN10200_OPERAND_MDR}, 103 104 /* Index register. */ 105 #define DI (MDR+1) 106 {2, 4, MN10200_OPERAND_DREG}, 107 108 /* 8 bit signed displacement, may promote to 16bit signed dispacement. */ 109 #define SD8 (DI+1) 110 {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 111 112 /* 16 bit signed displacement, may promote to 32bit dispacement. */ 113 #define SD16 (SD8+1) 114 {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 115 116 /* 8 bit pc-relative displacement. */ 117 #define SD8N_PCREL (SD16+1) 118 {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX}, 119 120 /* 8 bit signed immediate which may promote to 16bit signed immediate. */ 121 #define SIMM8 (SD8N_PCREL+1) 122 {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 123 124 /* 16 bit signed immediate which may promote to 32bit immediate. */ 125 #define SIMM16 (SIMM8+1) 126 {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE}, 127 128 /* 16 bit signed immediate which may not promote. */ 129 #define SIMM16N (SIMM16+1) 130 {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK}, 131 132 /* Either an open paren or close paren. */ 133 #define PAREN (SIMM16N+1) 134 {0, 0, MN10200_OPERAND_PAREN}, 135 136 /* dn register that appears in the first and second register positions. */ 137 #define DN01 (PAREN+1) 138 {2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED}, 139 140 /* an register that appears in the first and second register positions. */ 141 #define AN01 (DN01+1) 142 {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED}, 143 } ; 144 145 #define MEM(ADDR) PAREN, ADDR, PAREN 146 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 147 148 /* The opcode table. 150 151 The format of the opcode table is: 152 153 NAME OPCODE MASK { OPERANDS } 154 155 NAME is the name of the instruction. 156 OPCODE is the instruction opcode. 157 MASK is the opcode mask; this is used to tell the disassembler 158 which bits in the actual opcode must match OPCODE. 159 OPERANDS is the list of operands. 160 161 The disassembler reads the table in order and prints the first 162 instruction which matches, so this table is sorted to put more 163 specific instructions before more general instructions. It is also 164 sorted by major opcode. */ 165 166 const struct mn10200_opcode mn10200_opcodes[] = { 167 { "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}}, 168 { "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}}, 169 { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}}, 170 { "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}}, 171 { "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}}, 172 { "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}}, 173 { "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}}, 174 { "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}}, 175 { "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}}, 176 { "mov", 0x20, 0xf0, FMT_1, {MEM(AN1), DM0}}, 177 { "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}}, 178 { "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 179 { "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 180 { "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, 181 { "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, 182 { "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, 183 { "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}}, 184 { "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}}, 185 { "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}}, 186 { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}}, 187 { "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}}, 188 { "mov", 0xf7300000, 0xfffc0000, FMT_6, {MEM(IMM16_MEM), AN0}}, 189 { "mov", 0xf4d00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), AN0}}, 190 { "mov", 0x00, 0xf0, FMT_1, {DM0, MEM(AN1)}}, 191 { "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD8, AN1)}}, 192 { "mov", 0xf7800000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, 193 { "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, 194 { "mov", 0xf1c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, 195 { "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, 196 { "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, 197 { "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}}, 198 { "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM(AN1)}}, 199 { "mov", 0xf7a00000, 0xfff00000, FMT_6, {AM0, MEM2(SD16, AN1)}}, 200 { "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}}, 201 { "mov", 0xf180, 0xffc0, FMT_4, {AM0, MEM2(DI, AN1)}}, 202 { "mov", 0xf7200000, 0xfffc0000, FMT_6, {AN0, MEM(IMM16_MEM)}}, 203 { "mov", 0xf4500000, 0xfffc0000, FMT_7, {AN0, MEM(IMM24_MEM)}}, 204 { "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}}, 205 { "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 206 { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}}, 207 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 208 209 { "movx", 0xf57000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, 210 { "movx", 0xf7700000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 211 { "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 212 { "movx", 0xf55000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, 213 { "movx", 0xf7600000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, 214 { "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, 215 216 { "movb", 0xf52000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, 217 { "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 218 { "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 219 { "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, 220 { "movb", 0xf4c40000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, 221 { "movb", 0x10, 0xf0, FMT_1, {DM0, MEM(AN1)}}, 222 { "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}}, 223 { "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}}, 224 { "movb", 0xf4200000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}}, 225 { "movb", 0xf0c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}}, 226 { "movb", 0xc40000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}}, 227 { "movb", 0xf4440000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}}, 228 229 { "movbu", 0x30, 0xf0, FMT_1, {MEM(AN1), DM0}}, 230 { "movbu", 0xf53000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}}, 231 { "movbu", 0xf7500000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}}, 232 { "movbu", 0xf4900000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}}, 233 { "movbu", 0xf080, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}}, 234 { "movbu", 0xcc0000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}}, 235 { "movbu", 0xf4c80000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}}, 236 237 { "ext", 0xf3c1, 0xfff3, FMT_4, {DN1}}, 238 { "extx", 0xb0, 0xfc, FMT_1, {DN0}}, 239 { "extxu", 0xb4, 0xfc, FMT_1, {DN0}}, 240 { "extxb", 0xb8, 0xfc, FMT_1, {DN0}}, 241 { "extxbu", 0xbc, 0xfc, FMT_1, {DN0}}, 242 243 { "add", 0x90, 0xf0, FMT_1, {DN1, DM0}}, 244 { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}}, 245 { "add", 0xf2c0, 0xfff0, FMT_4, {AN1, DM0}}, 246 { "add", 0xf240, 0xfff0, FMT_4, {AN1, AM0}}, 247 { "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}}, 248 { "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, 249 { "add", 0xf4600000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 250 { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}}, 251 { "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}}, 252 { "add", 0xf4640000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 253 { "addc", 0xf280, 0xfff0, FMT_4, {DN1, DM0}}, 254 { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}}, 255 256 { "sub", 0xa0, 0xf0, FMT_1, {DN1, DM0}}, 257 { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}}, 258 { "sub", 0xf2d0, 0xfff0, FMT_4, {AN1, DM0}}, 259 { "sub", 0xf250, 0xfff0, FMT_4, {AN1, AM0}}, 260 { "sub", 0xf71c0000, 0xfffc0000, FMT_6, {IMM16, DN0}}, 261 { "sub", 0xf4680000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 262 { "sub", 0xf70c0000, 0xfffc0000, FMT_6, {IMM16, AN0}}, 263 { "sub", 0xf46c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 264 { "subc", 0xf290, 0xfff0, FMT_4, {DN1, DM0}}, 265 266 { "mul", 0xf340, 0xfff0, FMT_4, {DN1, DM0}}, 267 { "mulu", 0xf350, 0xfff0, FMT_4, {DN1, DM0}}, 268 269 { "divu", 0xf360, 0xfff0, FMT_4, {DN1, DM0}}, 270 271 { "cmp", 0xf390, 0xfff0, FMT_4, {DN1, DM0}}, 272 { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}}, 273 { "cmp", 0xf2e0, 0xfff0, FMT_4, {AN1, DM0}}, 274 { "cmp", 0xf260, 0xfff0, FMT_4, {AN1, AM0}}, 275 { "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}}, 276 { "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}}, 277 { "cmp", 0xf4780000, 0xfffc0000, FMT_7, {IMM24, DN0}}, 278 { "cmp", 0xec0000, 0xfc0000, FMT_3, {IMM16, AN0}}, 279 { "cmp", 0xf47c0000, 0xfffc0000, FMT_7, {IMM24, AN0}}, 280 281 { "and", 0xf300, 0xfff0, FMT_4, {DN1, DM0}}, 282 { "and", 0xf50000, 0xfffc00, FMT_5, {IMM8, DN0}}, 283 { "and", 0xf7000000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 284 { "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, 285 { "or", 0xf310, 0xfff0, FMT_4, {DN1, DM0}}, 286 { "or", 0xf50800, 0xfffc00, FMT_5, {IMM8, DN0}}, 287 { "or", 0xf7400000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 288 { "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}}, 289 { "xor", 0xf320, 0xfff0, FMT_4, {DN1, DM0}}, 290 { "xor", 0xf74c0000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 291 { "not", 0xf3e4, 0xfffc, FMT_4, {DN0}}, 292 293 { "asr", 0xf338, 0xfffc, FMT_4, {DN0}}, 294 { "lsr", 0xf33c, 0xfffc, FMT_4, {DN0}}, 295 { "ror", 0xf334, 0xfffc, FMT_4, {DN0}}, 296 { "rol", 0xf330, 0xfffc, FMT_4, {DN0}}, 297 298 { "btst", 0xf50400, 0xfffc00, FMT_5, {IMM8, DN0}}, 299 { "btst", 0xf7040000, 0xfffc0000, FMT_6, {SIMM16N, DN0}}, 300 { "bset", 0xf020, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, 301 { "bclr", 0xf030, 0xfff0, FMT_4, {DM0, MEM(AN1)}}, 302 303 { "beq", 0xe800, 0xff00, FMT_2, {SD8N_PCREL}}, 304 { "bne", 0xe900, 0xff00, FMT_2, {SD8N_PCREL}}, 305 { "blt", 0xe000, 0xff00, FMT_2, {SD8N_PCREL}}, 306 { "ble", 0xe300, 0xff00, FMT_2, {SD8N_PCREL}}, 307 { "bge", 0xe200, 0xff00, FMT_2, {SD8N_PCREL}}, 308 { "bgt", 0xe100, 0xff00, FMT_2, {SD8N_PCREL}}, 309 { "bcs", 0xe400, 0xff00, FMT_2, {SD8N_PCREL}}, 310 { "bls", 0xe700, 0xff00, FMT_2, {SD8N_PCREL}}, 311 { "bcc", 0xe600, 0xff00, FMT_2, {SD8N_PCREL}}, 312 { "bhi", 0xe500, 0xff00, FMT_2, {SD8N_PCREL}}, 313 { "bvc", 0xf5fc00, 0xffff00, FMT_5, {SD8N_PCREL}}, 314 { "bvs", 0xf5fd00, 0xffff00, FMT_5, {SD8N_PCREL}}, 315 { "bnc", 0xf5fe00, 0xffff00, FMT_5, {SD8N_PCREL}}, 316 { "bns", 0xf5ff00, 0xffff00, FMT_5, {SD8N_PCREL}}, 317 { "bra", 0xea00, 0xff00, FMT_2, {SD8N_PCREL}}, 318 319 { "beqx", 0xf5e800, 0xffff00, FMT_5, {SD8N_PCREL}}, 320 { "bnex", 0xf5e900, 0xffff00, FMT_5, {SD8N_PCREL}}, 321 { "bltx", 0xf5e000, 0xffff00, FMT_5, {SD8N_PCREL}}, 322 { "blex", 0xf5e300, 0xffff00, FMT_5, {SD8N_PCREL}}, 323 { "bgex", 0xf5e200, 0xffff00, FMT_5, {SD8N_PCREL}}, 324 { "bgtx", 0xf5e100, 0xffff00, FMT_5, {SD8N_PCREL}}, 325 { "bcsx", 0xf5e400, 0xffff00, FMT_5, {SD8N_PCREL}}, 326 { "blsx", 0xf5e700, 0xffff00, FMT_5, {SD8N_PCREL}}, 327 { "bccx", 0xf5e600, 0xffff00, FMT_5, {SD8N_PCREL}}, 328 { "bhix", 0xf5e500, 0xffff00, FMT_5, {SD8N_PCREL}}, 329 { "bvcx", 0xf5ec00, 0xffff00, FMT_5, {SD8N_PCREL}}, 330 { "bvsx", 0xf5ed00, 0xffff00, FMT_5, {SD8N_PCREL}}, 331 { "bncx", 0xf5ee00, 0xffff00, FMT_5, {SD8N_PCREL}}, 332 { "bnsx", 0xf5ef00, 0xffff00, FMT_5, {SD8N_PCREL}}, 333 334 { "jmp", 0xfc0000, 0xff0000, FMT_3, {IMM16_PCREL}}, 335 { "jmp", 0xf4e00000, 0xffff0000, FMT_7, {IMM24_PCREL}}, 336 { "jmp", 0xf000, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, 337 { "jsr", 0xfd0000, 0xff0000, FMT_3, {IMM16_PCREL}}, 338 { "jsr", 0xf4e10000, 0xffff0000, FMT_7, {IMM24_PCREL}}, 339 { "jsr", 0xf001, 0xfff3, FMT_4, {PAREN,AN1,PAREN}}, 340 341 { "nop", 0xf6, 0xff, FMT_1, {UNUSED}}, 342 343 { "rts", 0xfe, 0xff, FMT_1, {UNUSED}}, 344 { "rti", 0xeb, 0xff, FMT_1, {UNUSED}}, 345 346 /* Extension. We need some instruction to trigger "emulated syscalls" 347 for our simulator. */ 348 { "syscall", 0xf010, 0xffff, FMT_4, {UNUSED}}, 349 350 /* Extension. When talking to the simulator, gdb requires some instruction 351 that will trigger a "breakpoint" (really just an instruction that isn't 352 otherwise used by the tools. This instruction must be the same size 353 as the smallest instruction on the target machine. In the case of the 354 mn10x00 the "break" instruction must be one byte. 0xff is available on 355 both mn10x00 architectures. */ 356 { "break", 0xff, 0xff, FMT_1, {UNUSED}}, 357 358 { 0, 0, 0, 0, {0}}, 359 360 } ; 361 362 const int mn10200_num_opcodes = 363 sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]); 364 365 366
