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Searched
defs:rINST
(Results
1 - 10
of
10
) sorted by null
/art/runtime/interpreter/mterp/arm/
header.S
73
r7
rINST
first 16-bit code unit of current instruction
97
#define
rINST
r7
142
* Fetch the next instruction from rPC into
rINST
. Does not advance rPC.
145
ldrh
rINST
, [rPC]
161
ldrh
rINST
, [rPC, #((\count)*2)]!
166
* src and dest registers are parameterized (not hard-wired to rPC and
rINST
).
174
*
rINST
ahead of possible exception point. Be sure to manually advance rPC
178
ldrh
rINST
, [rPC, #((\count)*2)]
191
* We want to write "ldrh
rINST
, [rPC, _reg, lsl #1]!", but some of the
197
ldrh
rINST
, [rPC, \reg]
[
all
...]
/art/runtime/interpreter/mterp/mips64/
header.S
51
s3
rINST
first 16-bit code unit of current instruction
61
#define
rINST
s3
112
* Fetch the next instruction from rPC into
rINST
. Does not advance rPC.
115
lhu
rINST
, 0(rPC)
138
*
rINST
ahead of possible exception point. Be sure to manually advance rPC
142
lhu
rINST
, ((\count) * 2)(rPC)
149
and \reg,
rINST
, 255
/art/runtime/interpreter/mterp/x86/
header.S
160
#define
rINST
%ebx
215
* Refresh
rINST
.
216
* At enter to handler
rINST
does not contain the opcode number.
229
movzwl (rPC),
rINST
233
* Remove opcode from
rINST
, compute the address of handler and jump to it.
237
movzbl rINSTbh,
rINST
/art/runtime/interpreter/mterp/x86_64/
header.S
160
#define
rINST
%ebx
200
* Refresh
rINST
.
201
* At enter to handler
rINST
does not contain the opcode number.
218
* Remove opcode from
rINST
, compute the address of handler and jump to it.
222
movzbl rINSTbh,
rINST
/art/runtime/interpreter/mterp/out/
mterp_arm.S
80
r7
rINST
first 16-bit code unit of current instruction
104
#define
rINST
r7
149
* Fetch the next instruction from rPC into
rINST
. Does not advance rPC.
152
ldrh
rINST
, [rPC]
168
ldrh
rINST
, [rPC, #((\count)*2)]!
173
* src and dest registers are parameterized (not hard-wired to rPC and
rINST
).
181
*
rINST
ahead of possible exception point. Be sure to manually advance rPC
185
ldrh
rINST
, [rPC, #((\count)*2)]
198
* We want to write "ldrh
rINST
, [rPC, _reg, lsl #1]!", but some of the
204
ldrh
rINST
, [rPC, \reg]
[
all
...]
mterp_mips64.S
58
s3
rINST
first 16-bit code unit of current instruction
68
#define
rINST
s3
119
* Fetch the next instruction from rPC into
rINST
. Does not advance rPC.
122
lhu
rINST
, 0(rPC)
145
*
rINST
ahead of possible exception point. Be sure to manually advance rPC
149
lhu
rINST
, ((\count) * 2)(rPC)
156
and \reg,
rINST
, 255
384
FETCH_ADVANCE_INST 1 # advance rPC, load
rINST
385
GET_INST_OPCODE v0 # extract opcode from
rINST
394
ext a2,
rINST
, 8, 4 # a2 <-
[
all
...]
mterp_x86.S
167
#define
rINST
%ebx
222
* Refresh
rINST
.
223
* At enter to handler
rINST
does not contain the opcode number.
236
movzwl (rPC),
rINST
240
* Remove opcode from
rINST
, compute the address of handler and jump to it.
244
movzbl rINSTbh,
rINST
420
shrl $4,
rINST
#
rINST
<- B
421
GET_VREG
rINST
,
rINST
[
all
...]
mterp_x86_64.S
167
#define
rINST
%ebx
207
* Refresh
rINST
.
208
* At enter to handler
rINST
does not contain the opcode number.
225
* Remove opcode from
rINST
, compute the address of handler and jump to it.
229
movzbl rINSTbh,
rINST
398
movl
rINST
, %eax # eax <- BA
400
shrl $4,
rINST
#
rINST
<- B
446
movl
rINST
, %ecx # ecx <- BA
447
sarl $4,
rINST
# rINST <-
[
all
...]
mterp_mips.S
60
s4
rINST
first 16-bit code unit of current instruction
69
#define
rINST
s4
199
* Fetch the next instruction from rPC into
rINST
. Does not advance rPC.
201
#define FETCH_INST() lhu
rINST
, (rPC)
211
#define FETCH_ADVANCE_INST(_count) lhu
rINST
, ((_count)*2)(rPC); \
216
* src and dest registers are parameterized (not hard-wired to rPC and
rINST
).
224
*
rINST
ahead of possible exception point. Be sure to manually advance rPC
227
#define PREFETCH_INST(_count) lhu
rINST
, ((_count)*2)(rPC)
238
lhu
rINST
, (rPC)
259
#define GET_INST_OPCODE(rd) and rd,
rINST
, 0xF
[
all
...]
/art/runtime/interpreter/mterp/mips/
header.S
53
s4
rINST
first 16-bit code unit of current instruction
62
#define
rINST
s4
192
* Fetch the next instruction from rPC into
rINST
. Does not advance rPC.
194
#define FETCH_INST() lhu
rINST
, (rPC)
204
#define FETCH_ADVANCE_INST(_count) lhu
rINST
, ((_count)*2)(rPC); \
209
* src and dest registers are parameterized (not hard-wired to rPC and
rINST
).
217
*
rINST
ahead of possible exception point. Be sure to manually advance rPC
220
#define PREFETCH_INST(_count) lhu
rINST
, ((_count)*2)(rPC)
231
lhu
rINST
, (rPC)
252
#define GET_INST_OPCODE(rd) and rd,
rINST
, 0xF
[
all
...]
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