| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10200/ |
| shift.s | 4 ror d1 define
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10300/ |
| shift.s | 9 ror d1 define
|
| /device/google/contexthub/lib/nanohub/ |
| sha2.c | 39 #define ror(v, b) ({uint32_t ret; if (b) asm("ror %0, #" STRINGIFY(b) :"=r"(ret):"0"(v)); else ret = v; ret;}) macro
43 inline static uint32_t ror(uint32_t val, uint32_t by) function
76 uint32_t s0 = ror(state->w[i-15], 7) ^ ror(state->w[i-15], 18) ^ (state->w[i-15] >> 3);
77 uint32_t s1 = ror(state->w[i-2], 17) ^ ror(state->w[i-2], 19) ^ (state->w[i-2] >> 10);
93 uint32_t s1 = ror(e, 6) ^ ror(e, 11) ^ ror(e, 25)
[all...] |
| aes.c | 138 #define ror(v, b) ({uint32_t ret; if (b) asm("ror %0, #" STRINGIFY(b) :"=r"(ret):"0"(v)); else ret = v; ret;}) macro
142 inline static uint32_t ror(uint32_t val, uint32_t by) function
195 ror(RevTab0[FwdSbox[(encrK[j] >> 24) & 0xff]], 0) ^
196 ror(RevTab0[FwdSbox[(encrK[j] >> 16) & 0xff]], 8) ^
197 ror(RevTab0[FwdSbox[(encrK[j] >> 8) & 0xff]], 16) ^
198 ror(RevTab0[FwdSbox[(encrK[j] >> 0) & 0xff]], 24);
220 ror(FwdTab0[(x0 >> 24) & 0xff], 0) ^
221 ror(FwdTab0[(x1 >> 16) & 0xff], 8) ^
222 ror(FwdTab0[(x2 >> 8) & 0xff], 16)
[all...] |
| /system/core/libmincrypt/ |
| sha256.c | 36 #define ror(value, bits) (((value) >> (bits)) | ((value) << (32 - (bits)))) macro
72 uint32_t s0 = ror(W[t-15], 7) ^ ror(W[t-15], 18) ^ shr(W[t-15], 3);
73 uint32_t s1 = ror(W[t-2], 17) ^ ror(W[t-2], 19) ^ shr(W[t-2], 10);
87 uint32_t s0 = ror(A, 2) ^ ror(A, 13) ^ ror(A, 22);
90 uint32_t s1 = ror(E, 6) ^ ror(E, 11) ^ ror(E, 25)
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 32 ror, enumerator in enum:llvm::ARM_AM::ShiftOpc
51 case ARM_AM::ror: return "ror";
62 case ARM_AM::ror: return 3;
105 // reg [asr|lsl|lsr|ror|rrx] reg
106 // reg [asr|lsl|lsr|ror|rrx] imm
|
| /art/compiler/optimizing/ |
| instruction_simplifier.cc | 266 HRor* ror = new (GetGraph()->GetArena()) HRor(ushr->GetType(), ushr->GetLeft(), ushr->GetRight()); local
267 op->GetBlock()->ReplaceAndRemoveInstructionWith(op, ror);
296 // Shift distances are both constant, try replacing with Ror if they
320 // Ror dst, x, #rdist
342 // Ror dst, x, neg
350 // Ror dst, x, d
371 // Ror dst, x, d
380 // Ror dst, x, neg
1538 HRor* ror = new (GetGraph()->GetArena()) HRor(type, value, distance); local
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 37 ROR,
58 case AArch64_AM::ROR: return "ror";
79 case 3: return AArch64_AM::ROR;
94 /// 011 ==> ror
107 case AArch64_AM::ROR: STEnc = 3; break;
205 static inline uint64_t ror(uint64_t elt, unsigned size) { function in namespace:llvm::AArch64_AM
307 pattern = ror(pattern, size);
|
| /external/v8/src/x87/ |
| assembler-x87.cc | 979 void Assembler::ror(const Operand& dst, uint8_t imm8) { function in class:v8::internal::Assembler
[all...] |
| /external/valgrind/coregrind/ |
| m_transtab.c | 1367 UInt ror = 7; local
[all...] |
| /external/v8/src/ia32/ |
| assembler-ia32.cc | 1108 void Assembler::ror(const Operand& dst, uint8_t imm8) { function in class:v8::internal::Assembler
[all...] |
