| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_rename_regs.c | 72 unsigned writemask; local
86 writemask = rc_variable_writemask_sum(var);
87 rc_variable_change_dst(var, new_index, writemask);
|
| radeon_variable.c | 38 * Rewrite the index and writemask for the destination register of var
60 if (var_ptr->Dst.WriteMask == RC_MASK_W) {
156 unsigned int mask = var->Readers[i].WriteMask;
285 new->Dst.WriteMask = DstWriteMask;
320 unsigned int writemask; local
332 if (sub_inst->WriteMask) {
334 writemask = sub_inst->WriteMask;
337 writemask = sub_inst->OutputWriteMask;
339 writemask = 0
392 unsigned int writemask = 0; local
[all...] |
| radeon_pair_regalloc.c | 57 unsigned int Writemask;
238 unsigned int writemask,
248 if (classes[i].Writemasks[j] == writemask) {
281 unsigned int writemask = rc_variable_writemask_sum(variable); local
293 writemask = RC_MASK_XYZW;
299 class_index = find_class(classes, writemask, 3);
314 writemask, c.Writemasks[i]);
321 * then the writemask will be set to RC_MASK_XYZW
379 class_index = find_class(classes, writemask,
388 variable->Dst.Index, writemask);
615 unsigned int chan, class_id, writemask = 0; local
692 unsigned int writemask = reg_get_writemask(reg); local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_wm_pass1.c | 42 if (inst->writemask & (1<<i)) {
44 inst->writemask &= ~(1<<i);
50 return inst->writemask;
123 GLuint writemask; local
144 writemask = get_tracked_mask(c, inst);
145 if (!writemask) {
166 read0 = writemask;
180 read0 = writemask;
181 read1 = writemask;
186 read0 = writemask;
[all...] |
| brw_fs_vector_splitting.cpp | 273 unsigned int writemask; local
280 writemask = 1;
283 writemask = 1 << i;
296 NULL, writemask));
|
| brw_wm_pass0.c | 247 GLuint writemask )
253 if (writemask & (1<<i)) {
259 out->writemask = writemask;
317 GLuint writemask = inst->DstReg.WriteMask; local
341 pass0_set_dst(c, out, inst, writemask);
353 GLuint writemask = inst->DstReg.WriteMask; local
368 if (writemask & (1 << i)) {
[all...] |
| brw_disasm.c | 278 char *writemask[16] = { variable
572 err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
601 err |= control (file, "writemask", writemask, inst->bits1.da3src.dest_writemask, NULL);
[all...] |
| brw_eu.h | 90 GLuint writemask:4; /* dest only, align16 only */ member in struct:brw_reg::__anon19600::__anon19601
184 * \param writemask WRITEMASK_X/Y/Z/W bitfield
194 GLuint writemask )
217 * set swizzle and writemask to W, as the lower bits of subnr will
223 reg.dw1.bits.writemask = writemask;
531 /* If/else instructions break in align16 mode if writemask & swizzle
693 reg.dw1.bits.writemask &= mask;
701 reg.dw1.bits.writemask = mask;
967 GLuint writemask,
[all...] |
| brw_vec4.h | 136 dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
142 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in class:brw::dst_reg
|
| brw_vec4_visitor.cpp | 227 * writemask, note that uniform packing and register allocation
234 if (dst.writemask != WRITEMASK_XYZW) {
304 if (dst.writemask != WRITEMASK_XYZW) {
447 this->writemask = WRITEMASK_XYZW;
449 this->writemask = (1 << type->vector_elements) - 1;
808 dst.writemask = (1 << c->key.gl_fixed_input_size[i]) - 1;
862 reg->writemask = WRITEMASK_X;
865 reg->writemask = WRITEMASK_Y;
1048 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
1918 int writemask = intel->gen == 4 ? WRITEMASK_W : WRITEMASK_X; local
1963 int mrf, writemask; local
[all...] |
| brw_wm.h | 144 GLuint writemask:4; member in struct:brw_wm_instruction
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_aos.c | 323 * Writemask
326 if (reg->Register.WriteMask != TGSI_WRITEMASK_XYZW) {
327 LLVMValueRef writemask; local
329 writemask = lp_build_const_mask_aos_swizzled(bld->bld_base.base.gallivm,
331 reg->Register.WriteMask,
335 mask = LLVMBuildAnd(builder, mask, writemask, "");
337 mask = writemask;
471 * assume a full writemask and then let LLVM optimization passes eliminate
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_translate.c | 322 * Compute flags for saturation and writemask.
327 const uint writeMask
328 = inst->Dst[0].Register.WriteMask;
334 if (writeMask & TGSI_WRITEMASK_X)
336 if (writeMask & TGSI_WRITEMASK_Y)
338 if (writeMask & TGSI_WRITEMASK_Z)
340 if (writeMask & TGSI_WRITEMASK_W)
497 uint writemask; local
672 A0_DEST_CHANNEL_ALL, /* dest writemask */
687 A0_DEST_CHANNEL_ALL, /* dest writemask */
[all...] |
| i915_state.c | 446 int writemask = depth_stencil->stencil[0].writemask & 0xff; local
452 STENCIL_WRITE_MASK(writemask));
475 int wmask = depth_stencil->stencil[1].writemask & 0xff;
511 if (depth_stencil->depth.writemask)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_state.h | 61 uint8_t writemask[2]; member in struct:si_state_dsa
|
| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| lp_bld_depth.c | 276 if (stencil[0].writemask != 0xff ||
277 (stencil[1].enabled && front_facing != NULL && stencil[1].writemask != 0xff)) {
278 /* mask &= stencil[0].writemask */
279 LLVMValueRef writemask = lp_build_const_int_vec(bld->gallivm, bld->type, local
280 stencil[0].writemask);
281 if (stencil[1].enabled && stencil[1].writemask != stencil[0].writemask && front_facing != NULL) {
283 stencil[1].writemask);
284 writemask = lp_build_select(bld, front_facing, writemask, back_writemask)
[all...] |
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_text.c | 336 uint *writemask )
344 *writemask = TGSI_WRITEMASK_NONE;
348 *writemask |= TGSI_WRITEMASK_X;
352 *writemask |= TGSI_WRITEMASK_Y;
356 *writemask |= TGSI_WRITEMASK_Z;
360 *writemask |= TGSI_WRITEMASK_W;
363 if (*writemask == TGSI_WRITEMASK_NONE) {
364 report_error( ctx, "Writemask expected" );
371 *writemask = TGSI_WRITEMASK_XYZW;
683 uint writemask; local
1071 uint writemask; local
[all...] |
| tgsi_exec.c | 585 uint writemask = inst->Dst[0].Register.WriteMask; local
586 if (writemask == TGSI_WRITEMASK_X ||
587 writemask == TGSI_WRITEMASK_Y ||
588 writemask == TGSI_WRITEMASK_Z ||
589 writemask == TGSI_WRITEMASK_W ||
590 writemask == TGSI_WRITEMASK_NONE) {
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 593 // The writemask for AVX-512 instructions which is contained in EVEX.aaa
594 Reg writemask; member in struct:llvm::X86Disassembler::InternalInstruction
|
| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_context.h | 93 uint8_t writemask; member in struct:svga_blend_state::__anon19367
124 /* SVGA3D has one ref/mask/writemask triple shared between front &
|
| /external/mesa3d/src/gallium/include/pipe/ |
| p_state.h | 219 unsigned writemask:1; /**< allow depth buffer writes? */ member in struct:pipe_depth_state
232 unsigned writemask:8; member in struct:pipe_stencil_state
|
| /external/mesa3d/src/mesa/program/ |
| ir_to_mesa.cpp | 105 dst_reg(gl_register_file file, int writemask)
109 this->writemask = writemask;
118 this->writemask = 0;
127 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in class:dst_reg
146 this->writemask = WRITEMASK_XYZW;
399 assert(dst.writemask != 0);
435 int done_mask = ~dst.writemask;
469 inst->dst.writemask = this_mask;
513 int done_mask = ~dst.writemask;
[all...] |
| /external/mesa3d/src/gallium/drivers/r600/ |
| r600_pipe.h | 206 ubyte writemask[2]; member in struct:r600_pipe_dsa
305 ubyte writemask[2]; member in struct:r600_stencil_ref
|
| /external/mesa3d/src/mesa/state_tracker/ |
| st_glsl_to_tgsi.cpp | 148 st_dst_reg(gl_register_file file, int writemask, int type)
152 this->writemask = writemask;
163 this->writemask = 0;
172 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in class:st_dst_reg
194 this->writemask = WRITEMASK_XYZW;
596 assert(dst.writemask != 0);
708 int done_mask = ~dst.writemask;
742 inst->dst.writemask = this_mask;
798 int done_mask = ~dst.writemask;
[all...] |
| /toolchain/binutils/binutils-2.25/bfd/ |
| elf32-arm.c | 6818 unsigned int writemask = 0; local
[all...] |
