| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 72 unsigned BasePtr;
73 int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
78 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
88 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
110 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
118 .addReg(BasePtr).addImm(HighOffset).addReg(0);
124 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCLoopPreIncPrep.cpp | 123 static bool IsPtrInBounds(Value *BasePtr) {
124 Value *StrippedBasePtr = BasePtr;
311 Value *BasePtr = GetPointerOperand(MemI);
312 assert(BasePtr && "No pointer operand");
316 BasePtr->getType()->getPointerAddressSpace());
354 PtrInc->setIsInBounds(IsPtrInBounds(BasePtr));
364 if (PtrInc->getType() != BasePtr->getType())
365 NewBasePtr = new BitCastInst(PtrInc, BasePtr->getType(),
370 if (Instruction *IDel = dyn_cast<Instruction>(BasePtr))
372 BasePtr->replaceAllUsesWith(NewBasePtr)
[all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 47 /// BasePtr - X86 physical register used as a base ptr in complex stack
50 unsigned BasePtr;
133 unsigned getBaseRegister() const { return BasePtr; }
|
| X86RegisterInfo.cpp | 73 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
78 BasePtr = X86::ESI;
423 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64,
425 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
525 return MRI->canReserveReg(BasePtr);
544 unsigned BasePtr;
551 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
553 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
555 BasePtr = StackPtr;
557 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr)
[all...] |
| X86FrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 116 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP);
137 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
154 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
|
| /external/webrtc/webrtc/voice_engine/test/auto_test/ |
| voe_stress_test.cc | 120 VoEBase* base = _mgr.BasePtr();
195 VoEBase* base = _mgr.BasePtr();
305 VoEBase* base = _mgr.BasePtr();
388 VoEBase* base = _mgr.BasePtr();
|
| voe_output_test.cc | 80 VoEBase* base = manager_.BasePtr();
117 VoEBase* base = manager_.BasePtr();
|
| voe_cpu_test.cc | 48 VoEBase* base = _mgr.BasePtr();
|
| voe_standard_test.h | 137 VoEBase* BasePtr() const {
|
| /external/llvm/lib/CodeGen/ |
| ShadowStackGCLowering.cpp | 56 Type *Ty, Value *BasePtr, int Idx1,
59 Type *Ty, Value *BasePtr, int Idx1, int Idx2,
351 Value *BasePtr, int Idx,
357 Value *Val = B.CreateGEP(Ty, BasePtr, Indices, Name);
365 IRBuilder<> &B, Type *Ty, Value *BasePtr,
369 Value *Val = B.CreateGEP(Ty, BasePtr, Indices, Name);
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 81 /// BasePtr - ARM physical register used as a base ptr in complex stack
84 unsigned BasePtr;
153 unsigned getBaseRegister() const { return BasePtr; }
|
| ARMBaseRegisterInfo.cpp | 49 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {}
141 Reserved.set(BasePtr);
356 return MRI->canReserveReg(BasePtr);
|
| Thumb1FrameLowering.cpp | 109 unsigned BasePtr = RegInfo->getBaseRegister();
297 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
|
| ThumbRegisterInfo.cpp | 527 FrameReg = BasePtr;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 442 SDValue BasePtr = LD->getBasePtr();
448 if (DAG.isBaseWithConstantOffset(BasePtr) &&
449 isWordAligned(BasePtr->getOperand(0), DAG)) {
450 SDValue NewBasePtr = BasePtr->getOperand(0);
451 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
455 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) &&
458 BasePtr->getValueType(0));
466 BasePtr, LD->getPointerInfo(), MVT::i16,
469 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
485 // Lower to a call to __misaligned_load(BasePtr)
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopIdiomRecognize.cpp | 547 Value *BasePtr =
549 if (mayLoopAccessLocation(BasePtr, MRI_ModRef, CurLoop, BECount, StoreSize,
553 RecursivelyDeleteTriviallyDeadInstructions(BasePtr, TLI);
576 Builder.CreateMemSet(BasePtr, SplatValue, NumBytes, StoreAlignment);
594 NewCall = Builder.CreateCall(MSP, {BasePtr, PatternPtr, NumBytes});
[all...] |
| SROA.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 348 ConstantSDNode *BasePtr = dyn_cast<ConstantSDNode>(Ptr->getBasePtr());
349 assert(BasePtr);
364 uint64_t Index = BasePtr->getZExtValue();
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGClass.cpp | 773 llvm::Type *BasePtr = ConvertType(BaseElementTy);
774 BasePtr = llvm::PointerType::getUnqual(BasePtr);
775 Address BaseAddrPtr = Builder.CreateBitCast(LHS.getAddress(), BasePtr);
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | 794 APInt BasePtr(BitWidth, 0);
798 BasePtr = Base->getValue().zextOrTrunc(BitWidth);
802 if (Ptr->isNullValue() || BasePtr != 0) {
803 Constant *C = ConstantInt::get(Ptr->getContext(), Offset + BasePtr);
[all...] |
