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Searched
refs:CTX_PP_CNTL
(Results
1 - 10
of
10
) sorted by null
/external/mesa3d/src/mesa/drivers/dri/r200/
r200_fragshader.c
341
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] &= ~(R200_MULTI_PASS_ENABLE |
351
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] |= shader->numArithInstr[0] == 8 ?
355
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] |= R200_MULTI_PASS_ENABLE;
356
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] |= shader->numArithInstr[1] == 8 ?
388
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] |= R200_TEX_0_ENABLE << reg;
407
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] |= R200_TEX_0_ENABLE << reg;
469
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] |= R200_TEX_0_ENABLE << reg;
496
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] |= R200_TEX_0_ENABLE << reg;
r200_texstate.c
1003
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] &= ~(R200_TEX_BLEND_ENABLE_MASK | R200_MULTI_PASS_ENABLE);
1004
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] |= rmesa->state.envneeded << R200_TEX_BLEND_0_ENABLE_SHIFT;
1047
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] &= ~(R200_TEX_0_ENABLE << unit);
[
all
...]
r200_state.c
761
uint32_t p = rmesa->hw.ctx.cmd[
CTX_PP_CNTL
];
810
if ( rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] != p ) {
812
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] = p;
[
all
...]
r200_context.h
107
#define
CTX_PP_CNTL
9
r200_state_init.c
504
OUT_BATCH(atom->cmd[
CTX_PP_CNTL
]);
[
all
...]
/external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_state.c
563
uint32_t p = rmesa->hw.ctx.cmd[
CTX_PP_CNTL
];
626
if ( rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] != p ) {
628
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] = p;
[
all
...]
radeon_ioctl.c
105
OUT_BATCH(rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] | RADEON_SCISSOR_ENABLE);
116
OUT_BATCH(rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] & ~RADEON_SCISSOR_ENABLE);
radeon_context.h
98
#define
CTX_PP_CNTL
9
radeon_texstate.c
[
all
...]
radeon_state_init.c
386
OUT_BATCH(atom->cmd[
CTX_PP_CNTL
]);
700
rmesa->hw.ctx.cmd[
CTX_PP_CNTL
] = (RADEON_SCISSOR_ENABLE |
[
all
...]
Completed in 745 milliseconds