| /external/llvm/include/llvm/CodeGen/ |
| Analysis.h | 87 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
91 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
96 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
|
| ISDOpcodes.h | 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionOptimizer.cpp | 96 typedef std::tuple<int, unsigned, AArch64CC::CondCode> CmpInfo;
102 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
104 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
211 static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) {
225 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) {
256 AArch64CC::CondCode Cmp;
284 // Parse a condition code returned by AnalyzeBranch, and compute the CondCode
287 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
291 CC = (AArch64CC::CondCode)(int)Cond[0].getImm()
[all...] |
| AArch64ConditionalCompares.cpp | 165 AArch64CC::CondCode HeadCmpBBCC;
171 AArch64CC::CondCode CmpBBTailCC;
269 // Parse a condition code returned by AnalyzeBranch, and compute the CondCode
272 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
276 CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
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| AArch64BranchRelaxation.cpp | 356 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(0).getImm();
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| AArch64ISelLowering.cpp | [all...] |
| AArch64FastISel.cpp | 152 bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 38 enum CondCode {
137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
216 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
238 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
292 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
301 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
409 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()))
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_inlines.h | 26 static inline CondCode reverseCondCode(CondCode cc)
30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7));
33 static inline CondCode inverseCondCode(CondCode cc)
35 return static_cast<CondCode>(cc ^ 7);
|
| nv50_ir.h | 168 enum CondCode
587 bool compare(CondCode cc, float fval) const;
629 bool setPredicate(CondCode ccode, Value *);
679 CondCode cc;
826 void setCondition(CondCode cond) { setCond = cond; }
827 CondCode getCondition() const { return setCond; }
830 CondCode setCond;
|
| nv50_ir_build_util.h | 73 CmpInstruction *mkCmp(operation, CondCode, DataType,
80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
|
| nv50_ir_build_util.cpp | 223 BuildUtil::mkCmp(operation op, CondCode cc, DataType ty, Value *dst,
307 BuildUtil::mkFlow(operation op, void *targ, CondCode cc, Value *pred)
|
| nv50_ir.cpp | 459 ImmediateValue::compare(CondCode cc, float fval) const
464 switch (static_cast<CondCode>(cc & 7)) {
816 Instruction::setPredicate(CondCode ccode, Value *value)
|
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.h | 33 enum CondCode {
73 const char *MipsFCCToString(Mips::CondCode CC);
|
| MipsInstPrinter.cpp | 37 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
264 O << MipsFCCToString((Mips::CondCode)MO.getImm());
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 33 enum CondCode {
64 unsigned GetCondBranchFromCond(CondCode CC);
68 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
72 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
76 CondCode getCondFromCMovOpc(unsigned Opc);
80 CondCode GetOppositeBranchCondition(CondCode CC);
|
| /external/llvm/lib/CodeGen/ |
| Analysis.cpp | 163 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) {
185 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) {
200 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) {
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 193 enum CondCode { // Meaning (integer) Meaning (floating-point)
214 inline static const char *getCondCodeName(CondCode Code) {
236 inline static CondCode getInvertedCondCode(CondCode Code) {
239 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
246 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 673 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
686 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 192 unsigned CondCode = 0) const;
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 177 const ISD::CondCode Cond;
262 const ISD::CondCode Cond;
361 const ISD::CondCode Cond;
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 464 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
480 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
497 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
615 report_fatal_error("unimplemented select CondCode " + Twine(CC));
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 58 AArch64CC::CondCode parseCondCodeString(StringRef Cond);
201 AArch64CC::CondCode Code;
255 struct CondCodeOp CondCode;
287 CondCode = o.CondCode;
352 AArch64CC::CondCode getCondCode() const {
354 return CondCode.Code;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 319 void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
391 ISD::CondCode &CCCode, SDLoc dl);
545 ISD::CondCode &CCCode, SDLoc dl);
[all...] |
