| /toolchain/binutils/binutils-2.25/opcodes/ |
| m10300-opc.c | 53 #define DM2 (DM1+1)
57 #define AN0 (DM2+1)
489 { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
505 { "mov", 0xf540, 0xffc0, 0, FMT_D0, AM33, {DM2, RN0}},
651 { "movbu", 0xf440, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
698 { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
[all...] |
| rl78-decode.opc | 112 #define DM2(r1,r2,a) OPX (0, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
626 ID(mov); DM2(HL, B, 0); SR(A);
635 ID(mov); DM2(HL, C, 0); SR(A);
[all...] |
| rl78-decode.c | 113 #define DM2(r1,r2,a) OPX (0, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
[all...] |
