| /art/compiler/utils/arm/ |
| assembler_arm32.h | 157 void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
158 void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL) OVERRIDE;
160 void vmovd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
164 bool vmovd(DRegister dd, double d_imm, Condition cond = AL) OVERRIDE;
168 void vldrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
169 void vstrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
172 void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE
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| assembler_thumb2.h | 202 void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
203 void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL) OVERRIDE;
205 void vmovd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
209 bool vmovd(DRegister dd, double d_imm, Condition cond = AL) OVERRIDE;
213 void vldrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
214 void vstrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
217 void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE
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| constants_arm.h | 61 enum DRegister { // private marker to avoid generate-operator-out.py from processing.
98 std::ostream& operator<<(std::ostream& os, const DRegister& rhs);
396 DRegister DnField() const {
397 return static_cast<DRegister>(Bits(kRnShift, kRnBits) + (Bit(7) << 4));
399 DRegister DdField() const {
400 return static_cast<DRegister>(Bits(kRdShift, kRdBits) + (Bit(22) << 4));
402 DRegister DmField() const {
403 return static_cast<DRegister>(Bits(kRmShift, kRmBits) + (Bit(5) << 4));
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| assembler_arm.h | 623 virtual void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) = 0;
624 virtual void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL) = 0;
626 virtual void vmovd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
630 virtual bool vmovd(DRegister dd, double d_imm, Condition cond = AL) = 0;
634 virtual void vldrd(DRegister dd, const Address& ad, Condition cond = AL) = 0;
635 virtual void vstrd(DRegister dd, const Address& ad, Condition cond = AL) = 0;
638 virtual void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0
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| managed_register_arm.h | 61 // [S..D[ double precision VFP registers (enum DRegister)
73 // DRegister, VFPv3-D32 only)
83 // (enum SRegister), or a VFP double precision register (enum DRegister).
98 DRegister AsDRegister() const {
100 return static_cast<DRegister>(id_ - kNumberOfCoreRegIds - kNumberOfSRegIds);
105 DRegister d_reg = AsDRegister();
111 DRegister d_reg = AsDRegister();
154 // Returns true if this DRegister overlaps SRegisters.
195 static ArmManagedRegister FromDRegister(DRegister r) {
219 // Return a DRegister overlapping SRegister r_low and r_low + 1
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| assembler_arm32.cc | 343 void Arm32Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) {
363 bool Arm32Assembler::vmovd(DRegister dd, double d_imm, Condition cond) {
384 void Arm32Assembler::vaddd(DRegister dd, DRegister dn, DRegister dm,
396 void Arm32Assembler::vsubd(DRegister dd, DRegister dn, DRegister dm,
408 void Arm32Assembler::vmuld(DRegister dd, DRegister dn, DRegister dm
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| assembler_thumb2.cc | 438 inline int32_t Thumb2Assembler::VldrdEncoding32(DRegister dd, Register rn, int32_t offset) {
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| assembler_arm.cc | 60 std::ostream& operator<<(std::ostream& os, const DRegister& rhs) {
64 os << "DRegister[" << static_cast<int>(rhs) << "]";
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| managed_register_arm_test.cc | 125 TEST(ArmManagedRegister, DRegister) {
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| /art/compiler/utils/mips/ |
| constants_mips.h | 31 enum DRegister {
52 std::ostream& operator<<(std::ostream& os, const DRegister& rhs);
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| managed_register_mips.h | 67 // [F..D[ double precision FP registers (enum DRegister)
85 // FP register (enum DRegister), or a pair of core registers (enum RegisterPair).
100 DRegister AsDRegister() const {
102 return static_cast<DRegister>(id_ - kNumberOfCoreRegIds - kNumberOfFRegIds);
107 DRegister d_reg = AsDRegister();
113 DRegister d_reg = AsDRegister();
146 // Returns true if this DRegister overlaps FRegisters.
177 static MipsManagedRegister FromDRegister(DRegister r) {
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| assembler_mips.cc | 29 std::ostream& operator<<(std::ostream& os, const DRegister& rhs) {
33 os << "DRegister[" << static_cast<int>(rhs) << "]";
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| /art/compiler/utils/arm64/ |
| managed_register_arm64.h | 39 // [W..D[ double precision VFP registers (enum DRegister)
52 // * VFP double precision register (enum DRegister)
69 DRegister AsDRegister() const {
71 return static_cast<DRegister>(id_ - kNumberOfXRegIds - kNumberOfWRegIds);
96 DRegister AsOverlappingDRegister() const {
98 return static_cast<DRegister>(AsSRegister());
158 static Arm64ManagedRegister FromDRegister(DRegister r) {
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| assembler_arm64.h | 261 void StoreDToOffset(DRegister source, XRegister base, int32_t offset);
269 void LoadDFromOffset(DRegister dest, XRegister base, int32_t offset);
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| assembler_arm64.cc | 123 void Arm64Assembler::StoreDToOffset(DRegister source, XRegister base, int32_t offset) {
256 void Arm64Assembler::LoadDFromOffset(DRegister dest, XRegister base,
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| managed_register_arm64_test.cc | 167 TEST(Arm64ManagedRegister, DRegister) {
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| /art/runtime/arch/arm64/ |
| registers_arm64.cc | 56 std::ostream& operator<<(std::ostream& os, const DRegister& rhs) {
60 os << "DRegister[" << static_cast<int>(rhs) << "]";
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| registers_arm64.h | 113 enum DRegister {
149 std::ostream& operator<<(std::ostream& os, const DRegister& rhs);
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| /art/compiler/jni/quick/arm64/ |
| calling_convention_arm64.cc | 33 static const DRegister kDArgumentRegisters[] = {
41 static const DRegister kDCalleeSaveRegisters[] = {
173 Arm64ManagedRegister::FromDRegister(static_cast<DRegister>(d_reg)));
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| /art/compiler/jni/quick/arm/ |
| calling_convention_arm.cc | 38 static const DRegister kHFDArgumentRegisters[] = {
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| /art/compiler/jni/quick/mips/ |
| calling_convention_mips.cc | 28 static const DRegister kDArgumentRegisters[] = { D6, D7 };
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| /art/compiler/optimizing/ |
| code_generator_arm.h | 65 static constexpr DRegister FromLowSToD(SRegister reg) {
67 static_cast<DRegister>(reg / 2);
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| code_generator_arm.cc | 58 static constexpr DRegister DTMP = D31;
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| code_generator_arm64.cc | [all...] |
