| /external/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 183 /// instruction of itinerary class DefClass, operand index DefIdx can be
186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx,
190 if ((FirstDefIdx + DefIdx) >= LastDefIdx)
192 if (Forwardings[FirstDefIdx + DefIdx] == 0)
200 return Forwardings[FirstDefIdx + DefIdx] ==
207 int getOperandLatency(unsigned DefClass, unsigned DefIdx,
212 int DefCycle = getOperandCycle(DefClass, DefIdx);
222 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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| MCSubtargetInfo.h | 128 unsigned DefIdx) const {
129 assert(DefIdx < SC->NumWriteLatencyEntries &&
130 "MachineModel does not specify a WriteResource for DefIdx");
132 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
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| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 128 unsigned DefIdx = 0;
132 ++DefIdx;
134 return DefIdx;
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
189 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
192 STI->getWriteLatencyEntry(SCDesc, DefIdx);
208 // If DefIdx does not exist in the model (e.g. implicit defs), then return
214 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
228 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries
[all...] |
| PeepholeOptimizer.cpp | 296 unsigned DefIdx;
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
358 DefIdx = MRI.def_begin(Reg).getOperandNo();
363 /// the pair \p MI, \p DefIdx.
369 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
373 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
375 assert(DefIdx < Def->getDesc().getNumDefs() &&
376 Def->getOperand(DefIdx).isReg() && "Invalid definition");
377 Reg = Def->getOperand(DefIdx).getReg()
[all...] |
| TargetInstrInfo.cpp | [all...] |
| LiveRangeCalc.cpp | 46 SlotIndex DefIdx =
50 LR.createDeadDef(DefIdx, Alloc);
179 unsigned DefIdx;
182 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
185 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
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| LiveRangeEdit.cpp | 126 SlotIndex DefIdx;
128 DefIdx = LIS.getInstructionIndex(RM.OrigMI);
130 DefIdx = RM.ParentVNI->def;
131 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
140 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
|
| MachineVerifier.cpp | [all...] |
| TargetRegisterInfo.cpp | 306 unsigned SrcIdx, DefIdx;
309 SrcIdx, DefIdx) != nullptr;
|
| MachineInstr.cpp | 815 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
816 if (DefIdx != -1)
817 tieOperands(DefIdx, OpNo);
[all...] |
| RegisterCoalescer.cpp | 661 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
662 assert(DefIdx != -1);
664 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
770 SlotIndex DefIdx = UseIdx.getRegSlot();
771 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
774 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
775 assert(DVNI->def == DefIdx);
778 VNInfo *SubDVNI = S.getVNInfoAt(DefIdx);
[all...] |
| InlineSpiller.cpp | [all...] |
| RegAllocFast.cpp | 743 unsigned DefIdx = 0;
744 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
746 << DefIdx << ".\n");
[all...] |
| MachineLICM.cpp | 181 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 43 /// and \p DefIdx.
52 /// with the pair \p MI, \p DefIdx. False otherwise.
56 const MachineInstr &MI, unsigned DefIdx,
60 /// and \p DefIdx.
66 /// with the pair \p MI, \p DefIdx. False otherwise.
69 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
73 /// and \p DefIdx.
81 /// with the pair \p MI, \p DefIdx. False otherwise.
85 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
285 const MachineInstr *DefMI, unsigned DefIdx,
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 131 unsigned DefIdx;
149 return DefIdx-1;
|
| ScheduleDAGSDNodes.cpp | 554 DefIdx = 0;
560 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
568 for (;DefIdx < NodeNumDefs; ++DefIdx) {
569 if (!Node->hasAnyUseOfValue(DefIdx))
571 ValueType = Node->getSimpleValueType(DefIdx);
572 ++DefIdx;
634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 362 /// and \p DefIdx.
371 /// with the pair \p MI, \p DefIdx. False otherwise.
379 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
383 /// and \p DefIdx.
389 /// with the pair \p MI, \p DefIdx. False otherwise.
397 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
401 /// and \p DefIdx.
409 /// with the pair \p MI, \p DefIdx. False otherwise.
417 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 120 const MachineInstr *DefMI, unsigned DefIdx,
124 SDNode *DefNode, unsigned DefIdx,
126 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
132 unsigned DefIdx) const override {
|
| PPCVSXSwapRemoval.cpp | 617 int DefIdx = SwapMap[DefMI];
618 (void)EC->unionSets(SwapVector[DefIdx].VSEId,
621 DEBUG(dbgs() << format("Unioning %d with %d\n", SwapVector[DefIdx].VSEId,
695 int DefIdx = SwapMap[DefMI];
697 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
698 SwapVector[DefIdx].IsStore) {
704 DEBUG(dbgs() << " def " << DefIdx << ": ");
751 int DefIdx = SwapMap[DefMI];
752 SwapVector[DefIdx].WillRemove = 1
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 184 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
|
| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 203 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
204 DefIdx != DefEnd; ++DefIdx) {
207 DefIdx);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 206 unsigned DefIdx = 0;
210 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
211 IsTiedToChangedOp = OpChanged[DefIdx];
297 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
|
| /external/llvm/lib/CodeGen/MIRParser/ |
| MIParser.cpp | 887 unsigned DefIdx = Operands[I].TiedDefIdx.getValue();
888 if (DefIdx >= E)
891 Twine(DefIdx) + "'; instruction has only ") +
893 const auto &DefOperand = Operands[DefIdx].Operand;
898 Twine(DefIdx) + "'; the operand #" + Twine(DefIdx) +
902 if (TiedPair.first == DefIdx)
904 Twine("the tied-def operand #") + Twine(DefIdx) +
907 TiedRegisterPairs.push_back(std::make_pair(DefIdx, I));
[all...] |
