| /external/v8/src/mips/ |
| macro-assembler-mips.h | 648 DEFINE_INSTRUCTION(Divu);
656 DEFINE_INSTRUCTION2(Divu);
[all...] |
| macro-assembler-mips.cc | 1000 divu(rs, rt.rm());
1010 divu(rs, at);
1019 void MacroAssembler::Divu(Register rs, const Operand& rt) {
1021 divu(rs, rt.rm());
1026 divu(rs, at);
1031 void MacroAssembler::Divu(Register res, Register rs, const Operand& rt) {
1034 divu(rs, rt.rm());
1037 divu(res, rs, rt.rm());
1044 divu(rs, at);
1047 divu(res, rs, at)
[all...] |
| /external/v8/src/mips64/ |
| macro-assembler-mips64.h | 671 DEFINE_INSTRUCTION(Divu);
691 DEFINE_INSTRUCTION2(Divu);
[all...] |
| macro-assembler-mips64.cc | 1000 divu(rs, rt.rm());
1010 divu(rs, at);
1056 void MacroAssembler::Divu(Register rs, const Operand& rt) {
1058 divu(rs, rt.rm());
1063 divu(rs, at);
1068 void MacroAssembler::Divu(Register res, Register rs, const Operand& rt) {
1071 divu(rs, rt.rm());
1074 divu(res, rs, rt.rm());
1081 divu(rs, at);
1084 divu(res, rs, at)
[all...] |
| /external/v8/src/compiler/mips/ |
| code-generator-mips.cc | 813 __ Divu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
[all...] |
| /external/v8/src/compiler/mips64/ |
| code-generator-mips64.cc | 831 __ Divu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
[all...] |
