| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.h | 39 unsigned DstIdx;
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
106 unsigned getDstIdx() const { return DstIdx; }
|
| RegisterCoalescer.cpp | 305 SrcIdx = DstIdx = 0;
352 SrcIdx, DstIdx);
361 DstIdx = SrcSub;
374 if (DstIdx && !SrcIdx) {
376 std::swap(SrcIdx, DstIdx);
395 std::swap(SrcIdx, DstIdx);
419 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
434 TRI.composeSubRegIndices(DstIdx, DstSub);
[all...] |
| TwoAddressInstructionPass.cpp | 132 unsigned SrcIdx, unsigned DstIdx,
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
84 assert(DstIdx != -1);
85 MachineOperand &DstOp = MI.getOperand(DstIdx);
|
| R600Packetizer.cpp | 93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
94 if (DstIdx == -1) {
97 unsigned Dst = BI->getOperand(DstIdx).getReg();
|
| R600ISelLowering.cpp | 210 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
211 assert(DstIdx != -1);
215 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()) ||
[all...] |
| SIInstrInfo.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| DependenceAnalysis.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
