/external/llvm/lib/Target/AMDGPU/ |
SIFixSGPRCopies.cpp | 143 const TargetRegisterClass *DstRC = 148 return std::make_pair(SrcRC, DstRC); 152 const TargetRegisterClass *DstRC, 154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); 158 const TargetRegisterClass *DstRC, 160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); 193 const TargetRegisterClass *SrcRC, *DstRC; 194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); 196 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) 204 MRI.setRegClass(DstReg, DstRC); [all...] |
SILowerI1Copies.cpp | 107 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); 110 if (DstRC == &AMDGPU::VReg_1RegClass && 137 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
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SIInstrInfo.cpp | 493 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const { 495 if (DstRC->getSize() == 4) { 496 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; 497 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) { 499 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) { [all...] |
SIInstrInfo.h | 124 // \brief Returns an opcode that can be used to move a value to a \p DstRC 126 // DstRC, then AMDGPU::COPY is returned. 127 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
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/external/llvm/lib/Target/PowerPC/ |
PPCVSXCopy.cpp | 132 const TargetRegisterClass *DstRC = 142 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
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PPCVSXSwapRemoval.cpp | 857 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); 858 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 871 if (DstRC == &PPC::VRRCRegClass) { [all...] |
/external/llvm/utils/TableGen/ |
FastISelEmitter.cpp | 193 const CodeGenRegisterClass *DstRC = nullptr; 275 if (DstRC) { 276 if (DstRC != RC && !DstRC->hasSubClass(RC)) 279 DstRC = RC; 481 const CodeGenRegisterClass *DstRC = nullptr; 489 DstRC = &Target.getRegisterClass(Op0Rec); 490 if (!DstRC) 529 DstRC)) 580 DstRC, [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; 161 DstRC = MRI->getRegClass(VRBase); 164 DstRC = UseRC; 166 DstRC = TLI->getRegClassFor(VT); 175 VRBase = MRI->createVirtualRegister(DstRC); 333 const TargetRegisterClass *DstRC = nullptr; 335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 336 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 337 unsigned NewVReg = MRI->createVirtualRegister(DstRC); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.h | 180 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true 184 const TargetRegisterClass *DstRC,
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ARMBaseRegisterInfo.cpp | 758 const TargetRegisterClass *DstRC, 769 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) 777 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
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ARMFastISel.cpp | [all...] |
/external/llvm/lib/CodeGen/ |
RegisterCoalescer.cpp | 343 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); 351 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, 358 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); 362 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); 365 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); 380 CrossClass = NewRC != DstRC || NewRC != SrcRC; [all...] |
PeepholeOptimizer.cpp | 429 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); 430 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); 431 if (!DstRC) 537 MRI->constrainRegClass(DstReg, DstRC); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonGenInsert.cpp | 641 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR); 645 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC)) 648 if (DstRC != SrcRC) 650 if (DstRC == InsRC) 653 if (DstRC == &Hexagon::DoubleRegsRegClass) [all...] |
/external/llvm/include/llvm/Target/ |
TargetRegisterInfo.h | [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.cpp | [all...] |