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    Searched refs:FLD_Rm (Results 1 - 5 of 5) sorted by null

  /toolchain/binutils/binutils-2.25/opcodes/
aarch64-opc-2.c 30 {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
43 {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-point register"},
49 {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register"},
52 {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register"},
57 {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"},
aarch64-asm.c 513 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
592 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
594 insert_field (FLD_Rm, code, 0x1f, 0);
680 insert_field (FLD_Rm, code, info->reg.regno, 0);
701 insert_field (FLD_Rm, code, info->reg.regno, 0);
    [all...]
aarch64-opc.h 59 FLD_Rm,
aarch64-dis.c 849 info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
946 info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
1083 info->reg.regno = extract_field (FLD_Rm, code, 0);
1116 info->reg.regno = extract_field (FLD_Rm, code, 0);
    [all...]
aarch64-tbl.h     [all...]

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