| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 256 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
257 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
258 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
264 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
265 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
266 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 },
272 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
273 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
278 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
279 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }
[all...] |
| AArch64ISelLowering.cpp | 173 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
174 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
175 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
484 setTargetDAGCombine(ISD::FP_TO_SINT);
556 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
691 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 127 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
129 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
131 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
145 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
147 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
149 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
162 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
164 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
166 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
168 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }
[all...] |
| ARMISelLowering.cpp | 106 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
111 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
572 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
625 setTargetDAGCombine(ISD::FP_TO_SINT);
677 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
679 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 445 FP_TO_SINT,
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86IntrinsicsInfo.h | [all...] |
| X86TargetTransformInfo.cpp | 700 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 },
701 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
[all...] |
| X86ISelLowering.cpp | 202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 298 case ISD::FP_TO_SINT:
392 case ISD::FP_TO_SINT:
394 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
478 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
479 NewOpc = ISD::FP_TO_SINT;
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeVectorTypes.cpp | 89 case ISD::FP_TO_SINT:
440 case ISD::FP_TO_SINT:
645 case ISD::FP_TO_SINT:
[all...] |
| SelectionDAGDumper.cpp | 255 case ISD::FP_TO_SINT: return "fp_to_sint";
|
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 109 case ISD::FP_TO_SINT:
417 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
422 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
423 NewOpc = ISD::FP_TO_SINT;
[all...] |
| FastISel.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 417 ConversionOp = ISD::FP_TO_SINT;
492 Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32,
|
| AMDILISelLowering.cpp | 545 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 251 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
252 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
362 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
380 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
386 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
509 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
640 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
686 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
736 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
169 setTargetDAGCombine(ISD::FP_TO_SINT);
879 // we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint
881 case ISD::FP_TO_SINT: {
[all...] |
| AMDGPUISelLowering.cpp | 276 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
299 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
634 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 287 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
298 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
[all...] |
| MipsSEISelLowering.cpp | 279 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
