| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 259 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
260 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
261 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
267 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
268 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
269 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 },
274 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
275 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 },
281 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
282 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }
[all...] |
| AArch64ISelLowering.cpp | 176 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
177 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
178 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
485 setTargetDAGCombine(ISD::FP_TO_UINT);
557 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
692 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 128 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
130 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
132 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
146 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
148 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
150 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
163 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
165 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
167 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
169 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 }
[all...] |
| ARMISelLowering.cpp | 107 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
112 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
571 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
626 setTargetDAGCombine(ISD::FP_TO_UINT);
678 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
680 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 542 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
543 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 },
544 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 },
545 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 },
546 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 },
547 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 },
604 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
605 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
606 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 },
607 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }
[all...] |
| X86IntrinsicsInfo.h | [all...] |
| X86ISelLowering.cpp | 227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
245 // Expand FP_TO_UINT into a select
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 446 FP_TO_UINT,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 299 case ISD::FP_TO_UINT:
391 case ISD::FP_TO_UINT:
482 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
483 NewOpc = ISD::FP_TO_UINT;
[all...] |
| LegalizeVectorTypes.cpp | 90 case ISD::FP_TO_UINT:
441 case ISD::FP_TO_UINT:
646 case ISD::FP_TO_UINT:
[all...] |
| SelectionDAGDumper.cpp | 256 case ISD::FP_TO_UINT: return "fp_to_uint";
|
| LegalizeIntegerTypes.cpp | 110 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
416 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
420 if (N->getOpcode() == ISD::FP_TO_UINT &&
421 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
430 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 277 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
300 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
635 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
[all...] |
| R600ISelLowering.cpp | 85 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
87 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
873 case ISD::FP_TO_UINT:
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 363 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
368 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
373 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
374 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
381 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
387 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
510 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
641 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
687 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
737 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 332 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
[all...] |
| MipsSEISelLowering.cpp | 280 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 199 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
344 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
[all...] |
