| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 364 unsigned FirstReg = 0;
372 if (!FirstReg) FirstReg = R;
375 return FirstReg;
|
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 487 unsigned FirstReg = 0;
494 if (FirstReg != 0) {
496 State->UnionGroups(FirstReg, Reg);
499 FirstReg = Reg;
503 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| MipsISelLowering.h | 462 const Argument *FuncArg, unsigned FirstReg,
471 unsigned FirstReg, unsigned LastReg,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 765 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
771 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
772 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
774 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
776 unsigned OldFirstReg = FirstReg;
777 FirstReg = MRI.createVirtualRegister(FirstRC);
778 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
783 .addReg(FirstReg).addReg(SecondReg)
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
