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    Searched refs:HRI (Results 1 - 10 of 10) sorted by null

  /external/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp 301 auto &HRI = *HST.getRegisterInfo();
332 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
397 auto &HRI = *HST.getRegisterInfo();
407 insertCSRSpillsInBlock(*PrologB, CSI, HRI);
411 insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
416 insertCSRRestoresInBlock(B, CSI, HRI);
430 auto &HRI = *HST.getRegisterInfo();
449 unsigned SP = HRI.getStackRegister();
483 unsigned CallerSavedReg = HRI.getFirstCallerSavedNonParamReg();
509 auto &HRI = *HST.getRegisterInfo()
    [all...]
HexagonFrameLowering.h 89 const HexagonRegisterInfo &HRI) const;
91 const HexagonRegisterInfo &HRI) const;
HexagonGenMux.cpp 42 HexagonGenMux() : MachineFunctionPass(ID), HII(0), HRI(0) {
55 const HexagonRegisterInfo *HRI;
105 for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I)
144 unsigned NR = HRI->getNumRegs();
309 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
HexagonVLIWPacketizer.cpp 87 const HexagonRegisterInfo *HRI;
108 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
175 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
268 if (DepReg == HRI->getRARegister())
272 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())
276 const TargetRegisterClass* RC = HRI->getMinimalPhysRegClass(DepReg);
538 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
588 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
600 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst)
    [all...]
HexagonInstrInfo.cpp 113 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
114 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) &&
115 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg));
599 auto &HRI = getRegisterInfo();
660 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg),
662 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg),
684 HRI.getSubReg(DestReg, Hexagon::subreg_hireg)).
685 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg),
688 HRI.getSubReg(DestReg, Hexagon::subreg_loreg)).
689 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg)
    [all...]
HexagonVLIWPacketizer.h 41 const HexagonRegisterInfo *HRI;
HexagonGenInsert.cpp 469 HexagonGenInsert() : MachineFunctionPass(ID), HII(0), HRI(0) {
525 const HexagonRegisterInfo *HRI;
544 dbgs() << " " << PrintReg(I->first, HRI) << ":\n";
547 dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", "
548 << PrintRegSet(LL[i].second, HRI) << '\n';
762 dbgs() << LLVM_FUNCTION_NAME << ": " << PrintReg(VR, HRI)
763 << " AVs: " << PrintORL(AVs, HRI) << "\n";
826 dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n";
831 dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@"
879 dbgs() << PrintReg(VR, HRI) << " = insert(" << PrintReg(SrcR, HRI
    [all...]
HexagonBitSimplify.cpp     [all...]
HexagonISelLowering.cpp 712 auto &HRI = *Subtarget.getRegisterInfo();
714 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
    [all...]
HexagonISelDAGToDAG.cpp 54 const HexagonRegisterInfo *HRI;
59 HRI(nullptr) {
67 HRI = HST->getRegisterInfo();
    [all...]

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