| /external/llvm/include/llvm/Analysis/ |
| TargetTransformInfo.h | 312 bool HasBaseReg, int64_t Scale,
334 bool HasBaseReg, int64_t Scale,
570 int64_t BaseOffset, bool HasBaseReg,
578 int64_t BaseOffset, bool HasBaseReg,
694 bool HasBaseReg, int64_t Scale,
696 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
[all...] |
| TargetTransformInfoImpl.h | 206 bool HasBaseReg, int64_t Scale,
222 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {
224 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
410 bool HasBaseReg = (BaseGV == nullptr);
447 BaseOffset, HasBaseReg, Scale, AS)) {
|
| /external/llvm/lib/Analysis/ |
| TargetTransformInfo.cpp | 109 bool HasBaseReg,
112 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
134 bool HasBaseReg,
137 int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
|
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 250 bool HasBaseReg = BaseReg.getReg() != 0;
251 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") &&
253 HasBaseReg = false;
256 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
280 if (HasBaseReg)
|
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| NaryReassociate.cpp | 308 bool HasBaseReg = false;
314 HasBaseReg = true;
339 BaseOffset, HasBaseReg, Scale, AddrSpace);
|
| LoopStrengthReduce.cpp | 253 bool HasBaseReg;
280 : BaseGV(nullptr), BaseOffset(0), HasBaseReg(false), Scale(0),
369 HasBaseReg = true;
375 HasBaseReg = true;
480 if (HasBaseReg && BaseRegs.empty()) {
482 OS << "**error: HasBaseReg**";
483 } else if (!HasBaseReg && !BaseRegs.empty()) {
485 OS << "**error: !HasBaseReg**";
[all...] |
| StraightLineStrengthReduce.cpp | 243 bool HasBaseReg = false;
249 HasBaseReg = true;
274 BaseOffset, HasBaseReg, Scale, AddrSpace);
|
| /external/llvm/include/llvm/CodeGen/ |
| BasicTTIImpl.h | 122 bool HasBaseReg, int64_t Scale,
127 AM.HasBaseReg = HasBaseReg;
133 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {
137 AM.HasBaseReg = HasBaseReg;
|
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | [all...] |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 325 case 0: // r + i or just i, depending on HasBaseReg.
330 if (AM.HasBaseReg) {
396 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
399 if (AM.Scale == 1 && AM.HasBaseReg)
418 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
421 if (AM.Scale == 1 && AM.HasBaseReg)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
