| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 47 /// defined by an IMPLICIT_DEF, because it is commonly used to implement
51 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
52 IMPLICIT_DEF = 8,
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| TargetInstrInfo.h | 83 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
[all...] |
| /external/llvm/lib/CodeGen/ |
| ProcessImplicitDefs.cpp | 26 /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
27 /// for each use. Add isUndef marker to implicit_def defs and their uses.
89 DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
90 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
119 // If we found the using MI, we can erase the IMPLICIT_DEF.
127 // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
133 /// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
|
| MachineSSAUpdater.cpp | 110 /// InsertNewDef - Insert an empty PHI or IMPLICIT_DEF instruction which define
150 // Insert an implicit_def to represent an undef value.
151 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
283 /// GetUndefVal - Create an IMPLICIT_DEF instruction with a new register.
287 // Insert an implicit_def to represent an undef value.
288 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
|
| PHIElimination.cpp | 99 // Defs of PHI sources which are implicit_def.
157 // Remove dead IMPLICIT_DEF instructions.
212 /// are implicit_def's.
248 // If all sources of a PHI node are implicit_def, just emit an
249 // implicit_def instead of a copy.
251 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
389 // Insert an IMPLICIT_DEF instruction.
391 TII->get(TargetOpcode::IMPLICIT_DEF),
|
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SILowerI1Copies.cpp | 89 if (MI.getOpcode() == AMDGPU::IMPLICIT_DEF) {
|
| R600EmitClauseMarkers.cpp | 96 case AMDGPU::IMPLICIT_DEF:
|
| R600Packetizer.cpp | 355 if (MI->isKill() || MI->getOpcode() == AMDGPU::IMPLICIT_DEF ||
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| AMDGPUISelDAGToDAG.cpp | 342 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
392 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegStackify.cpp | 174 if (Def->getOpcode() == TargetOpcode::IMPLICIT_DEF)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 267 case TargetOpcode::IMPLICIT_DEF:
307 case TargetOpcode::IMPLICIT_DEF:
553 if (N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
|
| InstrEmitter.cpp | 211 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
212 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
286 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
287 // Add an IMPLICIT_DEF instruction before every use.
289 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
297 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
745 if (Opc == TargetOpcode::IMPLICIT_DEF)
746 // We want a unique VR for each IMPLICIT_DEF use.
[all...] |
| ScheduleDAGSDNodes.cpp | 82 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
537 if (POpc == TargetOpcode::IMPLICIT_DEF) {
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 766 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
821 case TargetOpcode::IMPLICIT_DEF:
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 57 case TargetOpcode::IMPLICIT_DEF:
109 case TargetOpcode::IMPLICIT_DEF:
|
| HexagonAsmPrinter.cpp | 579 MII->getOpcode() == TargetOpcode::IMPLICIT_DEF)
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 302 case TargetOpcode::IMPLICIT_DEF:
|
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 266 // See if the first operand of this insert_subreg is IMPLICIT_DEF
300 // See if all bar one of the operands are IMPLICIT_DEF and insert the
525 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
|
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 328 BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 617 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 892 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 763 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::i64), 0);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
