/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
arch-10.s | 55 # ABM/LZCNT 56 lzcnt %ecx,%ebx label
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x86-64-arch-2.s | 57 # ABM/LZCNT 58 lzcnt %ecx,%ebx label
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arch-10-1.l | 91 [ ]*55[ ]+\# ABM/LZCNT 92 [ ]*56[ ]+lzcnt %ecx,%ebx
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arch-10-2.l | 90 [ ]*55[ ]+\# ABM/LZCNT 91 [ ]*56[ ]+lzcnt %ecx,%ebx
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arch-10-3.l | 90 [ ]*55[ ]+\# ABM/LZCNT 91 [ ]*56[ ]+lzcnt %ecx,%ebx
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arch-10-4.l | 88 [ ]*55[ ]+\# ABM/LZCNT 89 [ ]*56[ ]+lzcnt %ecx,%ebx
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x86-64-arch-2-1.l | 91 [ ]*57[ ]+\# ABM/LZCNT 92 [ ]*58[ ]+lzcnt %ecx,%ebx
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x86-64-arch-2-2.l | 90 [ ]*57[ ]+\# ABM/LZCNT 91 [ ]*58[ ]+lzcnt %ecx,%ebx
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/external/v8/src/ |
globals.h | 737 LZCNT, [all...] |
/external/v8/test/cctest/ |
test-disasm-ia32.cc | 625 // LZCNT instructions 627 if (CpuFeatures::IsSupported(LZCNT)) { 628 CpuFeatureScope scope(&assm, LZCNT); 629 __ lzcnt(eax, ebx); 630 __ lzcnt(eax, Operand(ebx, ecx, times_4, 10000));
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test-disasm-x64.cc | 721 // LZCNT instructions 723 if (CpuFeatures::IsSupported(LZCNT)) { 724 CpuFeatureScope scope(&assm, LZCNT);
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test-assembler-ia32.cc | 1166 if (!CpuFeatures::IsSupported(LZCNT)) return; 1174 CpuFeatureScope fscope(&assm, LZCNT); 1182 __ lzcnt(ebx, ecx); 1187 __ lzcnt(ebx, Operand(esp, 0)); [all...] |
test-assembler-x64.cc | [all...] |
/external/v8/src/x64/ |
assembler-x64.cc | 95 if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT; 108 "SSE3=%d SSE4_1=%d SAHF=%d AVX=%d FMA3=%d BMI1=%d BMI2=%d LZCNT=%d " 113 CpuFeatures::IsSupported(BMI2), CpuFeatures::IsSupported(LZCNT), [all...] |
macro-assembler-x64.cc | [all...] |
/external/v8/src/ia32/ |
assembler-ia32.cc | 127 if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT; 140 "SSE3=%d SSE4_1=%d AVX=%d FMA3=%d BMI1=%d BMI2=%d LZCNT=%d POPCNT=%d " 145 CpuFeatures::IsSupported(LZCNT), CpuFeatures::IsSupported(POPCNT), 2812 void Assembler::lzcnt(Register dst, const Operand& src) { function in class:v8::internal::Assembler [all...] |
macro-assembler-ia32.cc | [all...] |