| /external/skia/tools/ |
| random_parse_path.cpp | 11 const struct Legal {
71 const Legal& legal = gLegal[index]; local
73 char symbol = legal.fSymbol | (rand->nextBool() ? 0x20 : 0);
77 for (int index = 0; index < legal.fScalars; ++index) {
81 if (rep < reps - 1 && index < legal.fScalars - 1) {
86 if ('A' == legal.fSymbol && 1 == index) {
|
| /external/icu/icu4c/source/test/intltest/ |
| transrt.cpp | 111 // Legal
114 class Legal {
116 Legal() {}
117 virtual ~Legal() {}
121 class LegalJamo : public Legal {
166 class LegalGreek : public Legal {
186 // A special case which is legal but should be
201 // Legal greek has breathing marks IFF there is a vowel or RHO at the start
342 Legal* legalSource; // NOT owned
363 Legal* adoptedLegal
976 Legal *legal = new Legal(); local
990 Legal *legal = new Legal(); local
999 Legal *legal = new Legal(); local
1014 Legal *legal = new LegalJamo(); local
1024 Legal *legal = new Legal(); local
1134 LegalGreek *legal = new LegalGreek(TRUE); local
1159 LegalGreek *legal = new LegalGreek(FALSE); local
1181 LegalGreek *legal = new LegalGreek(FALSE); local
1202 Legal *legal = new Legal(); local
1244 LegalHebrew* legal = new LegalHebrew(error); local
1257 Legal *legal = new Legal(); local
1356 Legal *legal = new LegalIndic(); local
1616 Legal *legal = new LegalIndic(); local
1617 test.test(UnicodeString(fromSet,""),UnicodeString(toSet,""),exclusions,this,quick,legal); local
1629 Legal *legal = new LegalIndic(); local
[all...] |
| /external/skia/fuzz/ |
| FuzzParsePath.cpp | 16 const struct Legal {
76 const Legal& legal = gLegal[index]; local
78 char symbol = legal.fSymbol | (fuzz->nextBool() ? 0x20 : 0);
82 for (int index = 0; index < legal.fScalars; ++index) {
86 if (rep < reps - 1 && index < legal.fScalars - 1) {
91 if ('A' == legal.fSymbol && 1 == index) {
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 69 setOperationAction(ISD::ADD, VecTys[i], Legal);
70 setOperationAction(ISD::SUB, VecTys[i], Legal);
71 setOperationAction(ISD::LOAD, VecTys[i], Legal);
72 setOperationAction(ISD::STORE, VecTys[i], Legal);
73 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
84 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
120 setOperationAction(ISD::MUL, MVT::i64, Legal);
160 setOperationAction(ISD::MUL, MVT::i32, Legal);
161 setOperationAction(ISD::MULHS, MVT::i32, Legal);
162 setOperationAction(ISD::MULHU, MVT::i32, Legal);
[all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| LoopVectorize.cpp | 321 TripCount(nullptr), VectorTripCount(nullptr), Legal(nullptr),
331 Legal = L;
553 LoopVectorizationLegality *Legal;
[all...] |
| /external/icu/android_icu4j/src/main/tests/android/icu/dev/test/translit/ |
| RoundTripTest.java | 129 .test(KATAKANA, "[" + HIRAGANA + LENGTH + "]", "[" + HALFWIDTH_KATAKANA + LENGTH + "]", this, new Legal());
136 .test("[a-zA-Z]", HIRAGANA, HIRAGANA_ITERATION, this, new Legal());
143 .test("[a-zA-Z]", KATAKANA, "[" + KATAKANA_ITERATION + HALFWIDTH_KATAKANA + "]", this, new Legal());
172 t.test("[a-zA-Z]", "[\uAC00-\uD7A4]", "", this, new Legal());
381 .test("[a-zA-Z\u0110\u0111\u02BA\u02B9]", "[\u0400-\u045F]", null, this, new Legal());
390 .test("[a-zA-Z\u02BE\u02BF]", ARABIC, "[a-zA-Z\u02BE\u02BF\u207F]", null, this, new Legal()); //
430 public static class LegalIndic extends Legal{
[all...] |
| /external/icu/icu4j/main/tests/translit/src/com/ibm/icu/dev/test/translit/ |
| RoundTripTest.java | 125 .test(KATAKANA, "[" + HIRAGANA + LENGTH + "]", "[" + HALFWIDTH_KATAKANA + LENGTH + "]", this, new Legal());
132 .test("[a-zA-Z]", HIRAGANA, HIRAGANA_ITERATION, this, new Legal());
139 .test("[a-zA-Z]", KATAKANA, "[" + KATAKANA_ITERATION + HALFWIDTH_KATAKANA + "]", this, new Legal());
168 t.test("[a-zA-Z]", "[\uAC00-\uD7A4]", "", this, new Legal());
377 .test("[a-zA-Z\u0110\u0111\u02BA\u02B9]", "[\u0400-\u045F]", null, this, new Legal());
386 .test("[a-zA-Z\u02BE\u02BF]", ARABIC, "[a-zA-Z\u02BE\u02BF\u207F]", null, this, new Legal()); //
426 public static class LegalIndic extends Legal{
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 168 // f32/f64 are legal, f80 is custom.
191 // f32 and f64 cases are Legal, f80 case is not
209 // are Legal, f80 is custom lowered.
215 // f32 and f64 cases are Legal, f80 case is not
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
276 // (low) operations are left as Legal, as there are single-result
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
315 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 85 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 35 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
37 setOperationAction(ISD::FRINT, MVT::f32, Legal);
|
| AMDILISelLowering.cpp | 180 setOperationAction(ISD::Constant , MVT::i64 , Legal);
194 setOperationAction(ISD::ConstantFP , MVT::f64 , Legal);
223 setOperationAction(ISD::ConstantFP , MVT::f32 , Legal);
224 setOperationAction(ISD::Constant , MVT::i32 , Legal);
|
| SIISelLowering.cpp | 44 setOperationAction(ISD::ADD, MVT::i64, Legal);
45 setOperationAction(ISD::ADD, MVT::i32, Legal);
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 74 setOperationAction(ISD::ADD, MVT::i32, Legal);
75 setOperationAction(ISD::ADDC, MVT::i32, Legal);
76 setOperationAction(ISD::ADDE, MVT::i32, Legal);
77 setOperationAction(ISD::SUBC, MVT::i32, Legal);
78 setOperationAction(ISD::SUBE, MVT::i32, Legal);
83 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
84 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
109 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
110 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
[all...] |
| AMDGPUISelLowering.cpp | 68 setOperationAction(ISD::Constant, MVT::i32, Legal);
69 setOperationAction(ISD::Constant, MVT::i64, Legal);
70 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
71 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
84 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
85 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
86 setOperationAction(ISD::FPOW, MVT::f32, Legal);
87 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
88 setOperationAction(ISD::FABS, MVT::f32, Legal);
89 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 87 Legal, // The target natively supports this operation.
94 /// This enum indicates whether a types are legal for a target, and if not,
220 // the constraint that all of the necessary shuffles are legal (as determined
389 /// The 'representative' register class is the largest legal super-reg
438 /// legal (return 'Legal') or we need to promote it to a larger type (return
461 /// the largest legal type it will be expanded to.
472 llvm_unreachable("Type is not legal nor is it to be expanded!");
477 /// Vector types are broken down into some number of legal first class types.
525 /// legal
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 129 setOperationAction(ISD::ConstantFP, T, Legal);
142 setOperationAction(Op, T, Legal);
144 setOperationAction(ISD::FMINNAN, T, Legal);
145 setOperationAction(ISD::FMAXNAN, T, Legal);
190 setOperationAction(ISD::TRAP, MVT::Other, Legal);
284 // Everything else is legal.
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 239 // happen by default if this wasn't a legal type)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 228 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
268 if (getOperationAction(Opcode, VT) == Legal)
280 // These operations are legal for anything that can be stored in a
284 setOperationAction(ISD::LOAD, VT, Legal);
285 setOperationAction(ISD::STORE, VT, Legal);
286 setOperationAction(ISD::VSELECT, VT, Legal);
287 setOperationAction(ISD::BITCAST, VT, Legal);
288 setOperationAction(ISD::UNDEF, VT, Legal);
301 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
302 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
175 setOperationAction(ISD::ROTL, MVT::i64, Legal);
176 setOperationAction(ISD::ROTR, MVT::i64, Legal);
182 setOperationAction(ISD::ROTL, MVT::i32, Legal);
183 setOperationAction(ISD::ROTR, MVT::i32, Legal);
235 // This is legal in NVPTX
236 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 116 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
117 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
149 setOperationAction(Opcode, VT, Legal);
480 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
630 // It is legal to extload from v4i8 to v4i16 or v4i32.
634 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
635 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
636 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
647 // operations, f64 is legal for the few double-precision instructions which
706 setIndexedLoadAction(im, MVT::i1, Legal);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 147 // Virtually no operation on f128 is legal, but LLVM can't expand them when
391 setOperationAction(ISD::FFLOOR, Ty, Legal);
392 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
393 setOperationAction(ISD::FCEIL, Ty, Legal);
394 setOperationAction(ISD::FRINT, Ty, Legal);
395 setOperationAction(ISD::FTRUNC, Ty, Legal);
396 setOperationAction(ISD::FROUND, Ty, Legal);
397 setOperationAction(ISD::FMINNUM, Ty, Legal);
398 setOperationAction(ISD::FMAXNUM, Ty, Legal);
399 setOperationAction(ISD::FMINNAN, Ty, Legal);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
40 /// For nodes that are of legal width, and that have more than one use, this
56 /// \brief Assuming the node is legal, "legalize" the results.
69 /// FSUB isn't legal.
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
98 /// \brief Expand bswap of vectors into a shuffle if legal.
208 case TargetLowering::Legal:
236 case TargetLowering::Legal
[all...] |
| LegalizeDAG.cpp | 240 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
[all...] |
| /external/opencv3/3rdparty/openexr/Imath/ |
| ImathEuler.h | 193 Legal = XYZ | XZY | YZX | YXZ | ZXY | ZYX |
240 static bool legal(Order);
766 Euler<T>::legal(typename Euler<T>::Order order) function in class:Imath::Euler
768 return (order & ~Legal) ? false : true;
|
