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    Searched refs:N_PHASES (Results 1 - 8 of 8) sorted by null

  /hardware/intel/img/hwcomposer/merrifield/ips/common/
OverlayHardware.h 36 #define N_PHASES 17
139 uint16_t Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES];
140 uint16_t RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
141 uint16_t Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES];
142 uint16_t RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
143 uint16_t UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES];
144 uint16_t RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
145 uint16_t UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES];
146 uint16_t RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
OverlayPlaneBase.cpp 916 double rawCoeff[MAX_TAPS * 32], coeffs[N_PHASES][MAX_TAPS];
940 for (i = 0; i < N_PHASES; i++) {
1001 coeffRec xcoeffY[N_HORIZ_Y_TAPS * N_PHASES];
1002 coeffRec xcoeffUV[N_HORIZ_UV_TAPS * N_PHASES];
    [all...]
  /hardware/intel/img/hwcomposer/moorefield_hdmi/ips/common/
OverlayHardware.h 36 #define N_PHASES 17
143 uint16_t Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES];
144 uint16_t RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
145 uint16_t Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES];
146 uint16_t RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
147 uint16_t UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES];
148 uint16_t RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
149 uint16_t UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES];
150 uint16_t RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
OverlayPlaneBase.cpp 896 double rawCoeff[MAX_TAPS * 32], coeffs[N_PHASES][MAX_TAPS];
920 for (i = 0; i < N_PHASES; i++) {
981 coeffRec xcoeffY[N_HORIZ_Y_TAPS * N_PHASES];
982 coeffRec xcoeffUV[N_HORIZ_UV_TAPS * N_PHASES];
1099 for (i = 0; i < N_PHASES; i++) {
    [all...]
  /hardware/intel/img/psb_video/src/
psb_overlay.h 171 #define N_PHASES 17
236 uint16_t Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
237 uint16_t RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
238 uint16_t Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
239 uint16_t RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
240 uint16_t UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
241 uint16_t RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
242 uint16_t UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
243 uint16_t RESERVEDG[0xa00 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
psb_overlay.c 334 double rawCoeff[MAX_TAPS * 32], coeffs[N_PHASES][MAX_TAPS];
358 for (i = 0; i < N_PHASES; i++) {
596 coeffRec xcoeffY[N_HORIZ_Y_TAPS * N_PHASES];
597 coeffRec xcoeffUV[N_HORIZ_UV_TAPS * N_PHASES];
701 for (i = 0; i < N_PHASES; i++) {
709 for (i = 0; i < N_PHASES; i++) {
    [all...]
  /hardware/intel/img/hwcomposer/merrifield/ips/anniedale/
AnnOverlayPlane.cpp 312 coeffRec xcoeffY[N_HORIZ_Y_TAPS * N_PHASES];
313 coeffRec xcoeffUV[N_HORIZ_UV_TAPS * N_PHASES];
314 coeffRec ycoeffY[N_VERT_Y_TAPS * N_PHASES];
315 coeffRec ycoeffUV[N_VERT_UV_TAPS * N_PHASES];
475 for (i = 0; i < N_PHASES; i++) {
484 for (i = 0; i < N_PHASES; i++) {
494 for (i = 0; i < N_PHASES; i++) {
503 for (i = 0; i < N_PHASES; i++) {
  /hardware/intel/img/hwcomposer/moorefield_hdmi/ips/anniedale/
AnnOverlayPlane.cpp 367 coeffRec xcoeffY[N_HORIZ_Y_TAPS * N_PHASES];
368 coeffRec xcoeffUV[N_HORIZ_UV_TAPS * N_PHASES];
369 coeffRec ycoeffY[N_VERT_Y_TAPS * N_PHASES];
370 coeffRec ycoeffUV[N_VERT_UV_TAPS * N_PHASES];
543 for (i = 0; i < N_PHASES; i++) {
552 for (i = 0; i < N_PHASES; i++) {
562 for (i = 0; i < N_PHASES; i++) {
571 for (i = 0; i < N_PHASES; i++) {

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