| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegisterInfo.cpp | 78 unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
79 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::CONST_I32), OffsetReg)
81 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::ADD_I32), OffsetReg)
83 .addReg(OffsetReg);
84 MI.getOperand(FIOperandNum).ChangeToRegister(OffsetReg, /*IsDef=*/false);
|
| WebAssemblyFrameLowering.cpp | 89 unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
90 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
96 .addReg(OffsetReg);
98 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
104 .addReg(OffsetReg)
150 unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
159 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
164 .addReg(OffsetReg);
165 // Re-use OffsetReg to hold the address of the stacktop
166 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstrInfo.cpp | 124 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
125 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
130 Address, OffsetReg);
138 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
139 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
145 OffsetReg);
|
| R600InstrInfo.h | 43 unsigned OffsetReg,
49 unsigned OffsetReg,
225 unsigned OffsetReg) const override;
230 unsigned OffsetReg) const override;
|
| AMDGPUInstrInfo.h | 177 unsigned OffsetReg) const = 0;
185 unsigned OffsetReg) const = 0;
|
| R600InstrInfo.cpp | [all...] |
| SIInstrInfo.h | 431 unsigned OffsetReg) const override;
437 unsigned OffsetReg) const override;
|
| SIInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 480 unsigned OffsetReg = 0;
484 OffsetReg = MI->getOperand(2).getReg();
519 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
522 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
[all...] |
| Thumb2InstrInfo.cpp | 533 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
534 if (OffsetReg != 0) {
|
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 194 unsigned OffsetReg;
250 return Mem.OffsetReg;
403 unsigned offsetReg = Op->getReg();
406 Op->Mem.OffsetReg = offsetReg;
415 Op->Mem.OffsetReg = Sparc::G0; // always 0
427 Op->Mem.OffsetReg = 0;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 685 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
693 unsigned OffsetReg = I->getOperand(0).getReg();
707 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
|
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 60 unsigned OffsetReg;
67 OffsetReg(0), Shift(0), Offset(0), GV(nullptr) { Base.Reg = 0; }
83 OffsetReg = Reg;
86 return OffsetReg;
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
