| /external/llvm/lib/Target/SystemZ/ |
| SystemZCallingConv.h | 58 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
62 for (unsigned i = 0; i < Outs.size(); ++i)
63 ArgIsFixed.push_back(Outs[i].IsFixed);
66 for (unsigned i = 0; i < Outs.size(); ++i)
67 ArgIsShortVector.push_back(IsShortVectorType(Outs[i].ArgVT));
69 CCState::AnalyzeCallOperands(Outs, Fn);
74 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
|
| SystemZISelLowering.h | 442 const SmallVectorImpl<ISD::OutputArg> &Outs,
445 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/Mips/ |
| MipsCCState.h | 38 void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
43 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
73 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
77 PreAnalyzeCallOperands(Outs, FuncArgs, CallNode);
78 CCState::AnalyzeCallOperands(Outs, Fn);
87 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
89 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
110 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
112 PreAnalyzeReturnForF128(Outs);
113 CCState::AnalyzeReturn(Outs, Fn)
[all...] |
| MipsCCState.cpp | 87 const SmallVectorImpl<ISD::OutputArg> &Outs) {
89 for (unsigned i = 0; i < Outs.size(); ++i) {
100 const SmallVectorImpl<ISD::OutputArg> &Outs,
103 for (unsigned i = 0; i < Outs.size(); ++i) {
105 originalTypeIsF128(FuncArgs[Outs[i].OrigArgIndex].Ty, CallNode));
107 FuncArgs[Outs[i].OrigArgIndex].Ty->isFloatingPointTy());
108 CallOperandIsFixed.push_back(Outs[i].IsFixed);
|
| MipsISelLowering.h | 497 const SmallVectorImpl<ISD::OutputArg> &Outs,
502 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 89 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
92 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
93 MVT VT = Outs[i].VT;
94 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
103 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
106 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
107 MVT VT = Outs[i].VT;
108 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
121 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
123 unsigned NumOps = Outs.size()
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.h | 64 const SmallVectorImpl<ISD::OutputArg> &Outs,
67 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| WebAssemblyISelLowering.cpp | 346 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
347 for (const ISD::OutputArg &Out : Outs) {
463 const SmallVectorImpl<ISD::OutputArg> &Outs,
466 return Outs.size() <= 1;
471 const SmallVectorImpl<ISD::OutputArg> &Outs,
474 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
483 for (const ISD::OutputArg &Out : Outs) {
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 133 const SmallVectorImpl<ISD::OutputArg> &Outs,
165 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| MSP430ISelLowering.cpp | 265 const SmallVectorImpl<ISD::OutputArg> &Outs) {
266 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
350 const SmallVectorImpl<ISD::OutputArg> &Outs) {
351 State.AnalyzeReturn(Outs, RetCC_MSP430);
394 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
412 Outs, OutVals, Ins, dl, DAG, InVals);
523 const SmallVectorImpl<ISD::OutputArg> &Outs,
531 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
539 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.h | 73 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| BPFISelLowering.cpp | 258 auto &Outs = CLI.Outs;
283 CCInfo.AnalyzeCallOperands(Outs, CC_BPF64);
287 if (Outs.size() >= 6) {
293 for (auto &Arg : Outs) {
389 const SmallVectorImpl<ISD::OutputArg> &Outs,
407 CCInfo.AnalyzeReturn(Outs, RetCC_BPF64);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 141 const SmallVectorImpl<ISD::OutputArg> &Outs,
146 const SmallVectorImpl<ISD::OutputArg> &Outs,
151 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| SparcISelLowering.cpp | 196 const SmallVectorImpl<ISD::OutputArg> &Outs,
200 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
201 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
207 const SmallVectorImpl<ISD::OutputArg> &Outs,
220 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
292 const SmallVectorImpl<ISD::OutputArg> &Outs,
303 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
739 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
755 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 110 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
157 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 156 const SmallVectorImpl<ISD::OutputArg> &Outs,
223 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | [all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 52 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 300 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
311 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 93 SmallVector<ISD::OutputArg, 4> Outs;
94 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
97 Fn->isVarArg(), Outs, Fn->getContext());
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 428 const SmallVectorImpl<ISD::OutputArg> &Outs,
447 const SmallVectorImpl<ISD::OutputArg> &Outs,
451 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 114 SmallVectorImpl<MachineInstr*> &Outs);
366 SmallVectorImpl<MachineInstr*> &Outs) {
400 Outs.push_back(MI);
|
| ARMISelLowering.h | 616 const SmallVectorImpl<ISD::OutputArg> &Outs,
623 const SmallVectorImpl<ISD::OutputArg> &Outs,
629 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 81 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
[all...] |
