| /frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm11_asm/ |
| h264bsd_interpolate_ver_half.s | 173 UXTB16 tmpa, tmp3, ROR #8 ;// |g4|g2|
174 UXTAB16 tmpa, tmpa, tmp4, ROR #8 ;// |g4+m4|g2+m2|
178 UXTB16 tmpb, tmp2, ROR #8 ;// |c4|c2|
180 UXTAB16 tmpb, tmpb, tmp5, ROR #8 ;// |c4+r4|c2+r2|
181 UXTAB16 tmpa, tmpa, tmp1, ROR #8 ;// 16+20(G+M)+A
182 UXTAB16 tmpa, tmpa, tmp6, ROR #8 ;// 16+20(G+M)+A+T
217 UXTB16 tmpa, tmp4, ROR #8 ;// |g4|g2|
218 UXTAB16 tmpa, tmpa, tmp5, ROR #8 ;// |g4+m4|g2+m2|
222 UXTB16 tmpb, tmp3, ROR #8 ;// |c4|c2|
224 UXTAB16 tmpb, tmpb, tmp6, ROR #8 ;// |c4+r4|c2+r2
[all...] |
| h264bsd_interpolate_ver_quarter.s | 174 UXTB16 tmpa, tmp3, ROR #8 ;// |g4|g2|
175 UXTAB16 tmpa, tmpa, tmp4, ROR #8 ;// |g4+m4|g2+m2|
179 UXTB16 tmpb, tmp2, ROR #8 ;// |c4|c2|
181 UXTAB16 tmpb, tmpb, tmp5, ROR #8 ;// |c4+r4|c2+r2|
182 UXTAB16 tmpa, tmpa, tmp1, ROR #8 ;// 16+20(G+M)+A
183 UXTAB16 tmpa, tmpa, tmp6, ROR #8 ;// 16+20(G+M)+A+T
226 UXTB16 tmpa, tmp4, ROR #8 ;// |g4|g2|
227 UXTAB16 tmpa, tmpa, tmp5, ROR #8 ;// |g4+m4|g2+m2|
231 UXTB16 tmpb, tmp3, ROR #8 ;// |c4|c2|
233 UXTAB16 tmpb, tmpb, tmp6, ROR #8 ;// |c4+r4|c2+r2
[all...] |
| h264bsd_interpolate_hor_ver_quarter.s | 180 UXTB16 x_3_1, x_3_1, ROR #8
184 UXTB16 x_7_5, x_7_5, ROR #8
220 UXTB16 x_3_1, x_3_1, ROR #8
338 UXTB16 tmpa, tmp3, ROR #8 ;// |g4|g2|
339 UXTAB16 tmpa, tmpa, tmp4, ROR #8 ;// |g4+m4|g2+m2|
343 UXTB16 tmpb, tmp2, ROR #8 ;// |c4|c2|
345 UXTAB16 tmpb, tmpb, tmp5, ROR #8 ;// |c4+r4|c2+r2|
346 UXTAB16 tmpa, tmpa, tmp1, ROR #8 ;// 16+20(G+M)+A
347 UXTAB16 tmpa, tmpa, tmp6, ROR #8 ;// 16+20(G+M)+A+T
389 UXTB16 tmpa, tmp4, ROR #8 ;// |g4|g2
[all...] |
| h264bsd_interpolate_mid_hor.s | 87 UXTB16 x_3_1, x_3_1, ROR #8
91 UXTB16 x_7_5, x_7_5, ROR #8
122 UXTB16 x_3_1, x_3_1, ROR #8
|
| h264bsd_interpolate_hor_half.s | 162 UXTB16 x_3_1, x_3_1, ROR #8
166 UXTB16 x_7_5, x_7_5, ROR #8
202 UXTB16 x_3_1, x_3_1, ROR #8
|
| h264bsd_interpolate_hor_quarter.s | 164 UXTB16 x_3_1, x_3_1, ROR #8
168 UXTB16 x_7_5, x_7_5, ROR #8
214 UXTB16 x_3_1, x_3_1, ROR #8
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| addthumb2err.s | 12 add sp, sp, r0, ROR #3
17 adds sp, sp, r0, ROR #3
22 sub sp, sp, r0, ROR #3
27 subs sp, sp, r0, ROR #3
|
| archv6.s | 51 sxtah r2, r4, r5, ROR #8
53 sxtahne r2, r4, r5, ROR #8
57 sxtab16 r2, r4, r5, ROR #8
59 sxtab16ne r2, r4, r5, ROR #8
61 sxtab r2, r4, r5, ROR #8
63 sxtabne r2, r4, r5, ROR #8
134 sxth r2, r5, ROR #8
136 sxthne r2, r5, ROR #8
138 sxtb16 r2, r5, ROR #8
140 sxtb16ne r2, r5, ROR #
[all...] |
| addthumb2err.l | 5 [^:]*:12: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ROR#3'
10 [^:]*:17: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,ROR#3'
15 [^:]*:22: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ROR#3'
20 [^:]*:27: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,ROR#3'
|
| inst.s | 203 mov r1, r2, ror #2
204 mov r1, r2, ror #31
205 mov r1, r2, ror r3
219 mov r1, r2, ROR #2
220 mov r1, r2, ROR #31
221 mov r1, r2, ROR r3
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.s | 121 UXTAB16 Temp1, ValC, ValD, ROR #8
122 UXTAB16 Temp3, ValE, ValB, ROR #8
124 UXTAB16 Acc0, ValA, ValF, ROR #8
130 UXTAB16 Temp1, ValE, ValD, ROR #8
131 UXTAB16 Temp3, ValC, ValF, ROR #8
135 UXTAB16 Acc1, ValG, ValB, ROR #8
139 UXTAB16 Acc2, ValC, ValH, ROR #8
148 UXTAB16 Temp1, ValG, ValD, ROR #8
149 UXTAB16 Acc3, ValI, ValD, ROR #8
150 UXTAB16 Temp2, ValE, ValF, ROR #
[all...] |
| armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.s | 124 UXTAB16 ValC1, r0x00ff00ff, ValC, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255]
127 UXTAB16 ValE1, r0x00ff00ff, ValE, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255]
129 UXTAB16 ValCD1, ValC1, ValD, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255] + [0 d3 0 d1]
134 UXTAB16 ValEB1, ValE1, ValB, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255] + [0 b3 0 b1]
138 UXTAB16 ValED1, ValE1, ValD, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255] + [0 d3 0 d1]
144 UXTAB16 ValCF1, ValC1, ValF, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255] + [0 f3 0 f1]
154 UXTAB16 ValA1, r0x00ff00ff, ValA, ROR #8 ;// [0 a3 0 a1] + [0 255 0 255]
156 UXTAB16 ValAF1, ValA1, ValF, ROR #8 ;// [0 a3 0 a1] + [0 255 0 255] + [0 f3 0 f1]
166 UXTAB16 ValG1, r0x00ff00ff, ValG, ROR #8 ;// [0 g3 0 g1] + [0 255 0 255]
168 UXTAB16 ValGB1, ValG1, ValB, ROR #8 ;// [0 g3 0 g1] + [0 255 0 255] + [0 b3 0 b1]
[all...] |
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 145 UXTAB16 Temp1, ValC, ValD, ROR #8
146 UXTAB16 Temp3, ValE, ValB, ROR #8
148 UXTAB16 Acc0, ValA, ValF, ROR #8
154 UXTAB16 Temp1, ValE, ValD, ROR #8
155 UXTAB16 Temp3, ValC, ValF, ROR #8
159 UXTAB16 Acc1, ValG, ValB, ROR #8
162 UXTAB16 Acc2, ValC, ValH, ROR #8
167 UXTAB16 Temp1, ValG, ValD, ROR #8
168 UXTAB16 Acc3, ValI, ValD, ROR #8
169 UXTAB16 Temp2, ValE, ValF, ROR #
[all...] |
| armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.s | 152 UXTAB16 ValC1, r0x00ff00ff, ValC, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255]
155 UXTAB16 ValE1, r0x00ff00ff, ValE, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255]
157 UXTAB16 ValCD1, ValC1, ValD, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255] + [0 d3 0 d1]
162 UXTAB16 ValEB1, ValE1, ValB, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255] + [0 b3 0 b1]
166 UXTAB16 ValED1, ValE1, ValD, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255] + [0 d3 0 d1]
171 UXTAB16 ValCF1, ValC1, ValF, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255] + [0 f3 0 f1]
181 UXTAB16 ValA1, r0x00ff00ff, ValA, ROR #8 ;// [0 a3 0 a1] + [0 255 0 255]
183 UXTAB16 ValAF1, ValA1, ValF, ROR #8 ;// [0 a3 0 a1] + [0 255 0 255] + [0 f3 0 f1]
191 UXTAB16 ValG1, r0x00ff00ff, ValG, ROR #8 ;// [0 g3 0 g1] + [0 255 0 255]
193 UXTAB16 ValGB1, ValG1, ValB, ROR #8 ;// [0 g3 0 g1] + [0 255 0 255] + [0 b3 0 b1]
[all...] |
| omxVCM4P10_FilterDeblockingLuma_VerEdge_I_s.s | 225 UXTAB16 tunpk0, tunpk0, row1, ROR#8
229 UXTAB16 tunpk2, tunpk2, row3, ROR#8
272 UXTAB16 tunpk4, tunpk4, row5, ROR#8
276 UXTAB16 tunpk6, tunpk6, row7, ROR#8
364 UXTAB16 tunpk0, tunpk0, P1b, ROR#8
369 UXTAB16 tunpk3, tunpk3, P3b, ROR#8
405 UXTAB16 tunpk0, tunpk0, Q0b, ROR#8
410 UXTAB16 tunpk3, tunpk3, Q2b, ROR#8
495 UXTAB16 tunpk1, tunpk1, P1a, ROR#8
502 UXTAB16 tunpk9, tunpk9, Q0a, ROR#
[all...] |
| omxVCM4P10_FilterDeblockingChroma_VerEdge_I_s.s | 192 UXTAB tunpk4, tunpk4, row5, ROR#8
196 UXTAB tunpk6, tunpk6, row7, ROR#8
228 UXTAB tunpk2, tunpk2, row1, ROR#8
233 UXTAB tunpk0, tunpk0, row3, ROR#8
|
| omxVCM4P10_PredictIntraChroma_8x8_s.s | 163 UXTB16 tVal8, tVal8, ROR #8 ;// pSrcAbove[1, 3]
167 UXTB16 tVal9, tVal9, ROR #8 ;// pSrcAbove[5, 7]
230 UXTB16 tVal8, tVal8, ROR #8 ;// pSrcAbove[1, 3]
234 UXTB16 tVal9, tVal9, ROR #8 ;// pSrcAbove[5, 7]
|
| omxVCM4P10_PredictIntra_16x16_s.s | 221 UXTB16 tVal8, tVal8, ROR #8 ;// pSrcAbove[1, 3]
222 UXTB16 tVal9, tVal9, ROR #8 ;// pSrcAbove[5, 7]
229 UXTB16 tVal10, tVal10, ROR #8 ;// pSrcAbove[9, 11]
230 UXTB16 tVal11, tVal11, ROR #8 ;// pSrcAbove[13, 15]
|
| /external/v8/test/mjsunit/compiler/ |
| rotate.js | 47 function ROR(x, sa) {
67 assertEquals(1 << ((2 % 32)), ROR(1, 30));
68 assertEquals(1 << ((2 % 32)), ROR(1, 30));
69 %OptimizeFunctionOnNextCall(ROR);
70 assertEquals(1 << ((2 % 32)), ROR(1, 30));
|
| /external/valgrind/none/tests/arm/ |
| v6media.stdout.exp | 85 uxtb r0, r1, ror #0 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
86 uxtb r0, r1, ror #8 :: rd 0x00000000 rm 0x000000ff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
87 uxtb r0, r1, ror #8 :: rd 0x000000ff rm 0x0000ff00, carryin 0, cpsr 0x00000000 ge[3:0]=0000
88 uxtb r0, r1, ror #16 :: rd 0x000000ff rm 0x00ff0000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
89 uxtb r0, r1, ror #24 :: rd 0x000000ff rm 0xff000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
91 uxtb16 r0, r1, ror #16 :: rd 0x00ff0000 rm 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
[all...] |
| /external/v8/src/parsing/ |
| token.h | 80 T(ROR, "rotate right", 11) /* only used by Crankshaft */ \
230 return BIT_OR <= op && op <= ROR;
|
| /system/core/libpixelflinger/codeflinger/ |
| load_store.cpp | 40 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 8));
42 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 8));
45 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 16));
|
| /external/boringssl/linux-arm/crypto/sha/ |
| sha1-armv4-large.S | 31 mov r5,r5,ror#30
32 mov r6,r6,ror#30
33 mov r7,r7,ror#30 @ [6]
39 add r7,r8,r7,ror#2 @ E+=K_00_19
44 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
48 add r7,r8,r7,ror#2 @ E+=K_00_19
50 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
55 and r10,r4,r10,ror#
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 37 ROR,
58 case AArch64_AM::ROR: return "ror";
79 case 3: return AArch64_AM::ROR;
94 /// 011 ==> ror
107 case AArch64_AM::ROR: STEnc = 3; break;
205 static inline uint64_t ror(uint64_t elt, unsigned size) { function in namespace:llvm::AArch64_AM
307 pattern = ror(pattern, size);
|
| /external/v8/test/cctest/ |
| test-disasm-arm.cc | 158 COMPARE(sbc(r7, r1, Operand(ip, ROR, 1), LeaveCC, hi),
159 "80c170ec sbchi r7, r1, ip, ror #1");
160 COMPARE(sbc(r7, r9, Operand(ip, ROR, 4)),
161 "e0c9726c sbc r7, r9, ip, ror #4");
164 COMPARE(sbc(r7, ip, Operand(ip, ROR, 31), SetCC, hi),
165 "80dc7fec sbchis r7, ip, ip, ror #31");
185 COMPARE(teq(r7, Operand(r5, ROR, r0), lt),
186 "b1370075 teqlt r7, r5, ror r0");
187 COMPARE(teq(r7, Operand(r6, ROR, lr)),
188 "e1370e76 teq r7, r6, ror lr")
[all...] |
