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Searched
refs:RegMask
(Results
1 - 14
of
14
) sorted by null
/external/llvm/include/llvm/CodeGen/
MachineOperand.h
159
const uint32_t *
RegMask
; // For MO_RegisterMask and MO_RegisterLiveOut.
471
/// clobbersPhysReg - Returns true if this
RegMask
clobbers PhysReg.
475
static bool clobbersPhysReg(const uint32_t *
RegMask
, unsigned PhysReg) {
478
return !(
RegMask
[PhysReg / 32] & (1u << PhysReg % 32));
481
/// clobbersPhysReg - Returns true if this
RegMask
operand clobbers PhysReg.
486
/// getRegMask - Returns a bit mask of registers preserved by this
RegMask
490
return Contents.
RegMask
;
496
return Contents.
RegMask
;
685
/// A
RegMask
operand represents a set of non-clobbered physical registers on
696
Op.Contents.
RegMask
= Mask
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MachineRegisterInfo.h
645
/// addPhysRegsUsedFromRegMask - Mark any registers not in
RegMask
as used.
647
void addPhysRegsUsedFromRegMask(const uint32_t *
RegMask
) {
648
UsedPhysRegMask.setBitsNotInMask(
RegMask
);
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...]
SelectionDAGNodes.h
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SelectionDAG.h
512
SDValue getRegisterMask(const uint32_t *
RegMask
);
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/toolchain/binutils/binutils-2.25/opcodes/
i386-opc.h
633
RegMask
,
755
unsigned int
regmask
:1;
member in struct:i386_operand_type::__anon75945
i386-gen.c
319
"
RegMask
" },
533
BITFIELD (
RegMask
),
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...]
/external/llvm/lib/CodeGen/
MIRPrinter.cpp
818
const uint32_t *
RegMask
= Op.getRegLiveOut();
822
if (
RegMask
[Reg / 32] & (1U << (Reg % 32))) {
PeepholeOptimizer.cpp
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/external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGRRList.cpp
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SelectionDAG.cpp
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/external/llvm/lib/Target/X86/
X86RegisterInfo.cpp
417
const uint32_t *
RegMask
= getCallPreservedMask(MF, CC);
418
if (MachineOperand::clobbersPhysReg(
RegMask
, getBaseRegister()))
X86FrameLowering.cpp
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...]
X86ISelLowering.cpp
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/external/llvm/lib/CodeGen/MIRParser/
MIParser.cpp
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