| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 45 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
342 ISD::SELECT_CC,
403 // We need all the operands of SELECT_CC to have the same value type, so if
406 // SELECT_CC node.
420 assert(!"Unhandled operand type parings in SELECT_CC");
431 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
466 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
472 // this SELECT_CC, so we must lower it
[all...] |
| SIISelLowering.cpp | 56 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
59 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
60 setTargetDAGCombine(ISD::SELECT_CC);
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
400 case ISD::SELECT_CC: {
|
| AMDILISelLowering.cpp | 170 setOperationAction(ISD::SELECT_CC, VT, Expand);
289 case ISD::SELECT_CC:
|
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.h | 29 SELECT_CC,
|
| BPFISelLowering.cpp | 109 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
178 case ISD::SELECT_CC:
507 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
518 case BPFISD::SELECT_CC:
519 return "BPFISD::SELECT_CC";
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 60 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
62 SELECT_CC,
|
| MSP430ISelLowering.cpp | 112 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
113 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
194 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 361 SELECT_CC,
567 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
171 setTargetDAGCombine(ISD::SELECT_CC);
601 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
[all...] |
| SIISelLowering.cpp | 101 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
102 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
103 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
104 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
195 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
262 setTargetDAGCombine(ISD::SELECT_CC);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 108 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N, ResNo); break;
661 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
[all...] |
| LegalizeTypesGeneric.cpp | 552 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0),
554 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0),
|
| SelectionDAGDumper.cpp | 216 case ISD::SELECT_CC: return "select_cc";
|
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 76 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
584 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
[all...] |
| LegalizeVectorTypes.cpp | 65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
345 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
595 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
[all...] |
| DAGCombiner.cpp | 711 // Return true if this node is a setcc, or is a select_cc
725 if (N.getOpcode() != ISD::SELECT_CC ||
[all...] |
| LegalizeVectorOps.cpp | 292 case ISD::SELECT_CC:
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 237 // PowerPC wants to turn select_cc of FP into fsel when possible.
238 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
239 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
441 setOperationAction(ISD::SELECT_CC, VT, Promote);
442 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 145 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
146 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
147 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
148 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
149 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
150 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
151 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 173 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 280 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
281 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
328 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
329 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 127 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
128 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
129 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
130 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
168 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
277 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
348 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
381 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
553 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
676 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 92 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
[all...] |
