| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 405 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
410 SIGN_EXTEND_INREG,
428 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
147 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal)
[all...] |
| SIISelLowering.cpp | 112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
114 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal)
[all...] |
| AMDGPUISelLowering.cpp | 618 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
645 case ISD::SIGN_EXTEND_INREG:
647 // sign_extend_inreg is the one to check for custom lowering. The extended
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 108 //FIXME: SIGN_EXTEND_INREG is not meaningful for floating point types
110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
218 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
|
| AMDGPUISelLowering.cpp | 92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 84 case ISD::SIGN_EXTEND_INREG:
456 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
551 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
635 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
[all...] |
| LegalizeVectorOps.cpp | 75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
326 case ISD::SIGN_EXTEND_INREG:
700 case ISD::SIGN_EXTEND_INREG:
[all...] |
| SelectionDAGDumper.cpp | 243 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
|
| DAGCombiner.cpp | [all...] |
| LegalizeTypes.h | 227 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
[all...] |
| LegalizeVectorTypes.cpp | 62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
325 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
607 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
[all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 159 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 136 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 162 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 533 IndexOpcode == ISD::SIGN_EXTEND_INREG)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
486 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
644 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
645 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
646 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
647 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
648 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 334 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
402 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
403 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| HexagonISelDAGToDAG.cpp | [all...] |
