| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 103 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
106 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
108 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
110 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
112 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
114 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
116 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
118 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
120 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
122 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }
[all...] |
| ARMISelLowering.cpp | 104 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
109 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
565 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
569 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
675 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 215 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
216 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
217 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
223 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
224 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
225 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
231 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
237 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 },
238 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }
[all...] |
| AArch64ISelLowering.cpp | 179 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
180 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
181 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
481 setTargetDAGCombine(ISD::SINT_TO_FP);
558 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
567 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
569 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
572 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
574 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
577 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 573 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
574 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 },
575 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 },
576 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
577 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
578 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 },
579 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
580 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
667 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
668 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }
[all...] |
| X86IntrinsicsInfo.h | 507 ISD::SINT_TO_FP, 0),
509 ISD::SINT_TO_FP, 0), // no rm
511 ISD::SINT_TO_FP, 0),
513 ISD::SINT_TO_FP, 0),
515 ISD::SINT_TO_FP, ISD::SINT_TO_FP), //er
[all...] |
| X86ISelLowering.cpp | 160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 402 SINT_TO_FP,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 339 case ISD::SINT_TO_FP:
387 case ISD::SINT_TO_FP:
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeFloatTypes.cpp | 109 case ISD::SINT_TO_FP:
[all...] |
| LegalizeVectorTypes.cpp | 97 case ISD::SINT_TO_FP:
442 case ISD::SINT_TO_FP:
652 case ISD::SINT_TO_FP:
[all...] |
| SelectionDAGDumper.cpp | 253 case ISD::SINT_TO_FP: return "sint_to_fp";
|
| FastISel.cpp | 244 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg,
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 527 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
530 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
|
| R600ISelLowering.cpp | 414 ConversionOp = ISD::SINT_TO_FP;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
255 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
364 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
371 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
388 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
511 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
638 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 275 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
309 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
632 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 281 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
[all...] |
