| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 404 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
408 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
412 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
416 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
421 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
425 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
429 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
433 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
|
| ARMISelLowering.cpp | 142 setOperationAction(ISD::SREM, VT, Expand);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 118 // TODO: Implement custom UREM/SREM routines
119 setOperationAction(ISD::SREM, VT, Expand);
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
655 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
673 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
|
| AMDGPUISelLowering.cpp | 90 case ISD::SREM: return LowerSREM(Op, DAG);
|
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | [all...] |
| MipsSEISelLowering.cpp | 170 setOperationAction(ISD::SREM, MVT::i32, Legal);
217 setOperationAction(ISD::SREM, MVT::i64, Legal);
267 setOperationAction(ISD::SREM, Ty, Legal);
[all...] |
| MipsISelLowering.cpp | 315 setOperationAction(ISD::SREM, MVT::i32, Expand);
319 setOperationAction(ISD::SREM, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 155 setOperationAction(ISD::SREM, MVT::i8, Expand);
161 setOperationAction(ISD::SREM, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 782 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
[all...] |
| SelectionDAGDumper.cpp | 182 case ISD::SREM: return "srem";
|
| LegalizeVectorOps.cpp | 266 case ISD::SREM:
[all...] |
| LegalizeVectorTypes.cpp | 125 case ISD::SREM:
685 case ISD::SREM:
[all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| FastISel.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 122 case ISD::SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
[all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 119 setOperationAction(ISD::SREM, MVT::i64, Expand);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| AArch64ISelLowering.cpp | 244 setOperationAction(ISD::SREM, MVT::i32, Expand);
245 setOperationAction(ISD::SREM, MVT::i64, Expand);
688 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 242 setOperationAction(ISD::SREM, VT, Expand);
313 setOperationAction(ISD::SREM, VT, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
