| /external/llvm/lib/MC/MCParser/ |
| MCTargetAsmParser.cpp | 15 const MCSubtargetInfo &STI)
17 STI(&STI)
26 STI = &STICopy;
31 return *STI;
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.h | 30 const MCSubtargetInfo &STI) override;
34 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
38 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
42 const MCSubtargetInfo &STI, raw_ostream &O);
44 const MCSubtargetInfo &STI, raw_ostream &O);
47 const MCSubtargetInfo &STI, raw_ostream &O);
49 const MCSubtargetInfo &STI, raw_ostream &O);
51 const MCSubtargetInfo &STI, raw_ostream &O);
53 const MCSubtargetInfo &STI, raw_ostream &O);
55 const MCSubtargetInfo &STI, raw_ostream &O)
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCShuffler.h | 30 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
32 : HexagonShuffler(MCII, STI) {
35 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
38 : HexagonShuffler(MCII, STI) {
56 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
58 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
60 unsigned HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
|
| HexagonMCCodeEmitter.h | 38 const MCSubtargetInfo &STI) const;
49 MCSubtargetInfo const &STI) const override;
53 const MCSubtargetInfo &STI,
60 MCSubtargetInfo const &STI) const;
65 MCSubtargetInfo const &STI) const;
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.h | 32 const MCSubtargetInfo &STI) override;
36 virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
38 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
42 const MCSubtargetInfo &STI,
51 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
54 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
56 void printHexImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
62 const MCSubtargetInfo &STI, raw_ostream &O) {
67 const MCSubtargetInfo &STI, raw_ostream &O);
69 const MCSubtargetInfo &STI, raw_ostream &O)
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.h | 40 bool isMicroMips(const MCSubtargetInfo &STI) const;
41 bool isMips32r6(const MCSubtargetInfo &STI) const;
51 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
56 const MCSubtargetInfo &STI) const override;
62 const MCSubtargetInfo &STI) const;
69 const MCSubtargetInfo &STI) const;
76 const MCSubtargetInfo &STI) const;
82 const MCSubtargetInfo &STI) const;
86 const MCSubtargetInfo &STI) const;
90 const MCSubtargetInfo &STI) const
[all...] |
| MipsMCCodeEmitter.cpp | 115 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
116 return STI.getFeatureBits()[Mips::FeatureMicroMips];
119 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
120 return STI.getFeatureBits()[Mips::FeatureMips32r6];
128 const MCSubtargetInfo &STI,
134 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
135 EmitInstruction(Val >> 16, 2, STI, OS);
136 EmitInstruction(Val, 2, STI, OS);
150 const MCSubtargetInfo &STI) const
173 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
[all...] |
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| SparcInstPrinter.h | 32 const MCSubtargetInfo &STI) override;
33 bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
35 bool isV9(const MCSubtargetInfo &STI) const;
38 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
40 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
44 const MCSubtargetInfo &STI, raw_ostream &O);
47 void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
49 void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
51 void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
53 bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
[all...] |
| SparcInstPrinter.cpp | 37 bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const {
38 return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0;
47 StringRef Annot, const MCSubtargetInfo &STI) {
48 if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O))
49 printInstruction(MI, STI, O);
54 const MCSubtargetInfo &STI,
75 O << "\tjmp "; printMemOperand(MI, 1, STI, O);
78 O << "\tcall "; printMemOperand(MI, 1, STI, O);
84 if (isV9(STI)
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| AMDGPUMCCodeEmitter.h | 33 const MCSubtargetInfo &STI) const;
37 const MCSubtargetInfo &STI) const {
43 const MCSubtargetInfo &STI) const {
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
| event2.s | 18 //STI Dreg ; /* previous state of IMASK restored from Dreg (a) */
19 STI R0;
20 STI R1;
21 STI R2;
|
| event2.d | 15 e: 40 00 STI R0;
16 10: 41 00 STI R1;
17 12: 42 00 STI R2;
|
| /external/llvm/include/llvm/MC/ |
| MCDisassembler.h | 56 MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
57 : Ctx(Ctx), STI(STI), Symbolizer(), CommentStream(nullptr) {}
86 const MCSubtargetInfo &STI;
104 const MCSubtargetInfo& getSubtargetInfo() const { return STI; }
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCCodeEmitter.cpp | 42 const MCSubtargetInfo &STI) const override;
48 const MCSubtargetInfo &STI) const;
54 const MCSubtargetInfo &STI) const;
62 const MCSubtargetInfo &STI) const;
65 const MCSubtargetInfo &STI) const;
68 const MCSubtargetInfo &STI) const;
71 const MCSubtargetInfo &STI) const;
74 const MCSubtargetInfo &STI) const;
77 const MCSubtargetInfo &STI) const;
91 const MCSubtargetInfo &STI) const
[all...] |
| /external/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| WebAssemblyMCCodeEmitter.cpp | 44 const MCSubtargetInfo &STI) const;
50 const MCSubtargetInfo &STI) const;
54 const MCSubtargetInfo &STI) const;
58 const MCSubtargetInfo &STI) const override;
70 const MCSubtargetInfo &STI) const {
87 const MCSubtargetInfo &STI) const {
95 const MCSubtargetInfo &STI) const {
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 53 const MCSubtargetInfo &STI) const;
56 const MCSubtargetInfo &STI) const;
59 const MCSubtargetInfo &STI) const;
62 const MCSubtargetInfo &STI) const;
65 const MCSubtargetInfo &STI) const;
68 const MCSubtargetInfo &STI) const;
71 const MCSubtargetInfo &STI) const;
74 const MCSubtargetInfo &STI) const;
77 const MCSubtargetInfo &STI) const;
80 const MCSubtargetInfo &STI) const
[all...] |
| /external/llvm/lib/Target/AMDGPU/Utils/ |
| AMDGPUBaseInfo.h | 49 bool isSI(const MCSubtargetInfo &STI);
50 bool isCI(const MCSubtargetInfo &STI);
51 bool isVI(const MCSubtargetInfo &STI);
54 /// \p STI otherwise return \p Reg.
55 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
|
| AMDGPUBaseInfo.cpp | 125 bool isSI(const MCSubtargetInfo &STI) {
126 return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
129 bool isCI(const MCSubtargetInfo &STI) {
130 return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
133 bool isVI(const MCSubtargetInfo &STI) {
134 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
137 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
142 assert(!isSI(STI));
143 return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
146 assert(!isSI(STI));
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.h | 32 const MCSubtargetInfo *&STI);
53 const MCSubtargetInfo *&STI);
55 X86AsmInstrumentation(const MCSubtargetInfo *&STI);
61 const MCSubtargetInfo *&STI;
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.h | 26 AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
27 : MCDisassembler(STI, Ctx) {}
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCTargetDesc.h | 32 const MCSubtargetInfo &STI,
36 const MCSubtargetInfo &STI,
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 50 const MCSubtargetInfo &STI) const;
56 const MCSubtargetInfo &STI) const;
64 const MCSubtargetInfo &STI) const;
70 const MCSubtargetInfo &STI) const;
76 const MCSubtargetInfo &STI) const;
82 const MCSubtargetInfo &STI) const;
88 const MCSubtargetInfo &STI) const;
95 const MCSubtargetInfo &STI) const;
101 const MCSubtargetInfo &STI) const;
107 const MCSubtargetInfo &STI) const
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 53 bool isThumb(const MCSubtargetInfo &STI) const {
54 return STI.getFeatureBits()[ARM::ModeThumb];
56 bool isThumb2(const MCSubtargetInfo &STI) const {
57 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
59 bool isTargetMachO(const MCSubtargetInfo &STI) const {
60 const Triple &TT = STI.getTargetTriple();
70 const MCSubtargetInfo &STI) const;
76 const MCSubtargetInfo &STI) const;
83 const MCSubtargetInfo &STI) const
[all...] |
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCCodeEmitter.cpp | 46 const MCSubtargetInfo &STI) const override;
52 const MCSubtargetInfo &STI) const;
58 const MCSubtargetInfo &STI) const;
62 const MCSubtargetInfo &STI) const;
65 const MCSubtargetInfo &STI) const;
68 const MCSubtargetInfo &STI) const;
71 const MCSubtargetInfo &STI) const;
84 const MCSubtargetInfo &STI) const {
85 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
105 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.h | 25 const MipsSubtarget &STI;
28 explicit MipsFrameLowering(const MipsSubtarget &sti, unsigned Alignment)
29 : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {}
|
