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    Searched refs:Src1Reg (Results 1 - 9 of 9) sorted by null

  /external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCCompound.cpp 84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
101 Src1Reg = MI.getOperand(1).getReg();
104 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
146 Src1Reg = MI.getOperand(1).getReg();
148 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
160 Src1Reg = MI.getOperand(0).getReg();
161 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)
HexagonMCDuplexInfo.cpp 181 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
320 Src1Reg = MCI.getOperand(0).getReg();
322 if (HexagonMCInstrInfo::isIntReg(Src1Reg) &&
324 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) {
328 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
336 Src1Reg = MCI.getOperand(0).getReg();
338 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
355 Src1Reg = MCI.getOperand(0).getReg();
357 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) &&
365 Src1Reg = MCI.getOperand(0).getReg()
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp     [all...]
  /external/llvm/lib/Target/ARM/
MLxExpansionPass.cpp 278 unsigned Src1Reg = MI->getOperand(2).getReg();
294 .addReg(Src1Reg, getKillRegState(Src1Kill))
  /external/llvm/lib/Target/AMDGPU/
R600InstrInfo.h 246 unsigned Src1Reg = 0) const;
R600InstrInfo.cpp     [all...]
SIInstrInfo.cpp     [all...]
  /external/llvm/lib/Target/AArch64/
AArch64FastISel.cpp     [all...]
  /external/llvm/lib/Target/Mips/
MipsFastISel.cpp 981 unsigned Src1Reg = getRegForValue(SI->getTrueValue());
985 if (!Src1Reg || !Src2Reg || !CondReg)
1003 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
    [all...]

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