| /external/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 135 const TargetRegisterClass *SrcRC =
141 // SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg());
148 return std::make_pair(SrcRC, DstRC);
151 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC,
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC);
157 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC,
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC);
193 const TargetRegisterClass *SrcRC, *DstRC;
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI)
[all...] |
| SILowerI1Copies.cpp | 108 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg());
111 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
138 SrcRC == &AMDGPU::VReg_1RegClass) {
|
| SIRegisterInfo.h | 97 const TargetRegisterClass *SrcRC,
|
| SIRegisterInfo.cpp | 483 const TargetRegisterClass *SrcRC,
501 return getCommonSubClass(DefRC, SrcRC) != nullptr;
|
| SIInstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetRegisterInfo.cpp | 299 const TargetRegisterClass *SrcRC,
302 if (DefRC == SrcRC)
308 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
316 std::swap(DefRC, SrcRC);
321 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
324 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
329 const TargetRegisterClass *SrcRC,
332 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
|
| RegisterCoalescer.cpp | 342 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
351 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
358 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
362 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
365 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
380 CrossClass = NewRC != DstRC || NewRC != SrcRC;
[all...] |
| PeepholeOptimizer.cpp | 685 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
686 ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC,
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
40 if (DestRC->getSize() != SrcRC->getSize())
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
55 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
58 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXCopy.cpp | 107 const TargetRegisterClass *SrcRC =
116 unsigned NewVReg = MRI.createVirtualRegister(SrcRC);
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 180 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true
182 const TargetRegisterClass *SrcRC,
|
| ARMBaseRegisterInfo.cpp | 756 const TargetRegisterClass *SrcRC,
769 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
775 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
|
| ARMFastISel.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 495 // subreg index DefSubReg, reading from another source with class SrcRC and
500 const TargetRegisterClass *SrcRC,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 389 const TargetRegisterClass *SrcRC,
392 CopyFromSU->CopySrcRC = SrcRC;
397 CopyToSU->CopyDstRC = SrcRC;
|
| InstrEmitter.cpp | 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
171 if (MatchReg && SrcRC->getCopyCost() < 0) {
[all...] |
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonGenInsert.cpp | 642 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR);
645 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC))
648 if (DstRC != SrcRC)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
