| /art/compiler/optimizing/ |
| intrinsics_mips.cc | 268 __ Srl(out, out, 24);
282 __ Srl(out, in, 16);
288 __ Srl(out, out, 8);
299 __ Srl(out, out, 4);
305 __ Srl(out, out, 2);
311 __ Srl(out, out, 1);
334 __ Srl(AT, in_lo, 16);
339 __ Srl(out_lo, in_hi, 16); // Here we are finally done reading
347 __ Srl(TMP, TMP, 8);
353 __ Srl(out_lo, out_lo, 8)
[all...] |
| code_generator_mips.cc | [all...] |
| code_generator_mips64.cc | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 351 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
355 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
357 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
387 // Look for (and (srl X, c1), c2).
388 SDValue Srl = N1.getOperand(0);
390 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
409 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 505 case ISD::SRL:
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips_test.cc | 362 TEST_F(AssemblerMIPSTest, Srl) {
363 DriverStr(RepeatRRIb(&mips::MipsAssembler::Srl, 5, "srl ${reg1}, ${reg2}, {imm}"), "Srl");
[all...] |
| assembler_mips.h | 168 void Srl(Register rd, Register rt, int shamt);
[all...] |
| assembler_mips.cc | 372 void MipsAssembler::Srl(Register rd, Register rt, int shamt) {
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | [all...] |
| assembler_mips64.h | 165 void Srl(GpuRegister rd, GpuRegister rt, int shamt);
|
| assembler_mips64.cc | 344 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) {
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| X86ISelLowering.cpp | 462 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
[all...] |
