/external/llvm/lib/Target/AArch64/ |
AArch64AdvSIMDScalarPass.cpp | 112 static bool isGPR64(unsigned Reg, unsigned SubReg, 114 if (SubReg) 121 static bool isFPR64(unsigned Reg, unsigned SubReg, 125 SubReg == 0) || 127 SubReg == AArch64::dsub); 129 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || 130 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); 137 unsigned &SubReg) { 138 SubReg = 0; 146 SubReg = AArch64::dsub [all...] |
AArch64ISelDAGToDAG.cpp | 552 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); 554 dl, MVT::i32, N, SubReg); 761 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); 765 TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg); [all...] |
AArch64InstrInfo.cpp | [all...] |
/external/llvm/lib/CodeGen/ |
LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; 199 MachineInstr *Def = PhysRegDef[SubReg]; 204 LastDefReg = SubReg; 252 unsigned SubReg = *SubRegs; 253 if (Processed.count(SubReg)) 255 if (PartDefRegs.count(SubReg)) 259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, 262 PhysRegDef[SubReg] = LastPartialDef; 263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) 291 unsigned SubReg = *SubRegs [all...] |
PeepholeOptimizer.cpp | 160 bool findNextSource(unsigned Reg, unsigned SubReg, 225 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) { 226 addSource(Reg, SubReg); 256 assert(Idx < getNumSources() && "SubReg source out of index"); 257 return RegSrcs[Idx].SubReg; 406 /// result, then replace all reachable uses of the source with the subreg of the 607 /// for the value defined by \p Reg and \p SubReg. 614 /// share the same register file as \p Reg and \p SubReg. The client should 617 bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg, 628 TargetInstrInfo::RegSubRegPair CurSrcPair(Reg, SubReg); [all...] |
LiveRangeCalc.cpp | 65 unsigned SubReg = MO.getSubReg(); 66 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { 67 LaneBitmask Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) 159 unsigned SubReg = MO.getSubReg(); 160 if (SubReg != 0) { 161 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg);
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MachineInstrBundle.cpp | 187 unsigned SubReg = *SubRegs; 188 if (LocalDefSet.insert(SubReg).second) 189 LocalDefs.push_back(SubReg);
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VirtRegMap.cpp | 316 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in 378 unsigned SubReg = MO.getSubReg(); 379 if (SubReg != 0) { 414 PhysReg = TRI->getSubReg(PhysReg, SubReg); 415 assert(PhysReg && "Invalid SubReg for physical register");
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LiveIntervalAnalysis.cpp | 66 "enable-subreg-liveness", cl::Hidden, cl::init(true), 206 && "Separated components should only occur for unused subreg defs"); 543 unsigned SubReg = MO.getSubReg(); 544 if (SubReg != 0) { 545 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); [all...] |
LiveRangeEdit.cpp | 180 // FIXME: Targets don't know how to fold subreg uses. 228 unsigned SubReg = MO.getSubReg(); 229 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
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TargetInstrInfo.cpp | [all...] |
/external/llvm/lib/MC/ |
MCRegisterInfo.cpp | 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { 39 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); 44 if (*Subs == SubReg)
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/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | 165 /// expected the pre-extension value is available as a subreg of the result 263 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 344 /// Used to give some type checking when modeling Reg:SubReg. 347 unsigned SubReg; 348 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0) 349 : Reg(Reg), SubReg(SubReg) {} 356 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0, 358 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} 364 /// the list is modeled as <Reg:SubReg, SubIdx> [all...] |
TargetRegisterInfo.h | 246 const char *const *SubRegIndexNames; // Names of subreg indexes. 495 // subreg index DefSubReg, reading from another source with class SrcRC and 528 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 533 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. [all...] |
/external/llvm/lib/Target/AMDGPU/ |
SIRegisterInfo.cpp | 239 unsigned SubReg = NumSubRegs > 1 ? 244 .addReg(SubReg, getDefRegState(IsLoad)) 280 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), 293 .addReg(SubReg) 313 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), 325 SubReg)
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SIFixSGPRCopies.cpp | 200 unsigned SubReg = CopyUse.getOperand(1).getSubReg(); 201 if (SubReg != AMDGPU::NoSubRegister)
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SILowerControlFlow.cpp | 409 unsigned SubReg = TRI->getSubReg(VecReg, AMDGPU::sub0); 410 if (!SubReg) 411 SubReg = VecReg; 413 const TargetRegisterClass *RC = TRI->getPhysRegClass(SubReg); 414 int RegIdx = TRI->getHWRegIndex(SubReg) + Offset;
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R600OptimizeVectorRegisters.cpp | 12 /// common data and/or have enough undef subreg using swizzle abilities. 192 unsigned SubReg = (*It).first; 199 .addReg(SubReg) 201 UpdatedRegToChan[SubReg] = Chan;
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SIInstrInfo.cpp | 953 unsigned SubReg = Src0.getSubReg(); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.h | 183 unsigned SubReg,
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/external/llvm/include/llvm/CodeGen/ |
MachineInstrBuilder.h | 66 unsigned SubReg = 0) const { 76 SubReg,
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MachineOperand.h | 72 /// MO_Register has no subReg. 347 void setSubReg(unsigned subReg) { 349 SubReg_TargetFlags = subReg; 350 assert(SubReg_TargetFlags == subReg && "SubReg out of range"); 354 /// subregister Reg:SubReg. Take any existing SubReg index into account, 355 /// using TargetRegisterInfo to compose the subreg indices if necessary. 361 /// Reg, taking any existing SubReg into account. For instance, 601 unsigned SubReg = 0 [all...] |
/external/llvm/lib/CodeGen/MIRParser/ |
MIParser.cpp | 120 bool parseSubRegisterIndex(unsigned &SubReg); 853 bool MIParser::parseSubRegisterIndex(unsigned &SubReg) { 859 SubReg = getSubRegIndex(Name); 860 if (!SubReg) 930 unsigned SubReg = 0; 932 if (parseSubRegisterIndex(SubReg)) 944 Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug, [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelLowering.h | 525 bool ClearEven, unsigned SubReg) const;
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/external/llvm/lib/Target/Mips/ |
MipsSEInstrInfo.cpp | 596 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); 622 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
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