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    Searched refs:TargetRegisterClass (Results 1 - 25 of 231) sorted by null

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  /external/mesa3d/src/gallium/drivers/radeon/
SIRegisterInfo.h 39 virtual const TargetRegisterClass *
40 getISARegClass(const TargetRegisterClass * rc) const;
48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
R600RegisterInfo.h 36 virtual const TargetRegisterClass * getISARegClass(
37 const TargetRegisterClass * rc) const;
47 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
AMDGPURegisterInfo.h 44 virtual const TargetRegisterClass * getISARegClass(
45 const TargetRegisterClass * rc) const {
49 virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
SIRegisterInfo.cpp 42 const TargetRegisterClass *
43 SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
52 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
  /external/llvm/lib/Target/AMDGPU/
SIRegisterInfo.h 57 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
60 bool isSGPRClass(const TargetRegisterClass *RC) const {
76 bool hasVGPRs(const TargetRegisterClass *RC) const;
81 static bool isPseudoRegClass(const TargetRegisterClass *RC) {
86 const TargetRegisterClass *getEquivalentVGPRClass(
87 const TargetRegisterClass *SRC) const;
92 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
95 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
97 const TargetRegisterClass *SrcRC
    [all...]
R600RegisterInfo.h 38 const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
41 getRegClassWeight(const TargetRegisterClass *RC) const override;
SIFixSGPRCopies.cpp 128 static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
135 const TargetRegisterClass *SrcRC =
143 const TargetRegisterClass *DstRC =
151 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC,
152 const TargetRegisterClass *DstRC,
157 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC,
158 const TargetRegisterClass *DstRC,
193 const TargetRegisterClass *SrcRC, *DstRC;
220 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg)
    [all...]
  /external/llvm/lib/Target/X86/
X86RegisterInfo.h 65 const TargetRegisterClass *
66 getMatchingSuperRegClass(const TargetRegisterClass *A,
67 const TargetRegisterClass *B,
70 const TargetRegisterClass *
71 getSubClassWithSubReg(const TargetRegisterClass *RC,
74 const TargetRegisterClass *
75 getLargestLegalSuperClass(const TargetRegisterClass *RC,
78 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
80 const TargetRegisterClass *
87 const TargetRegisterClass *
    [all...]
  /external/llvm/include/llvm/CodeGen/
RegisterClassInfo.h 67 void compute(const TargetRegisterClass *RC) const;
70 const RCInfo &get(const TargetRegisterClass *RC) const {
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
103 bool isProperSubClass(const TargetRegisterClass *RC) const {
119 unsigned getMinCost(const TargetRegisterClass *RC) {
127 unsigned getLastCostChange(const TargetRegisterClass *RC) {
MachineSSAUpdater.h 27 class TargetRegisterClass;
48 const TargetRegisterClass *VRC;
LiveStackAnalysis.h 41 std::map<int, const TargetRegisterClass *> S2RCMap;
58 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
76 const TargetRegisterClass *getIntervalRegClass(int Slot) const {
78 std::map<int, const TargetRegisterClass *>::const_iterator I =
  /external/llvm/lib/Target/ARM/
ThumbRegisterInfo.h 30 const TargetRegisterClass *
31 getLargestLegalSuperClass(const TargetRegisterClass *RC,
34 const TargetRegisterClass *
57 const TargetRegisterClass *RC,
ARMBaseRegisterInfo.h 112 const TargetRegisterClass *
115 const TargetRegisterClass *
116 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
118 const TargetRegisterClass *
119 getLargestLegalSuperClass(const TargetRegisterClass *RC,
122 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
182 const TargetRegisterClass *SrcRC,
184 const TargetRegisterClass *DstRC,
186 const TargetRegisterClass *NewRC) const override;
Thumb1InstrInfo.h 48 const TargetRegisterClass *RC,
54 const TargetRegisterClass *RC,
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 56 class TargetRegisterClass {
61 typedef const TargetRegisterClass* const * sc_iterator;
120 /// Return true if this TargetRegisterClass has the ValueType vt.
140 /// Return true if the specified TargetRegisterClass
141 /// is a proper sub-class of this TargetRegisterClass.
142 bool hasSubClass(const TargetRegisterClass *RC) const {
147 bool hasSubClassEq(const TargetRegisterClass *RC) const {
152 /// Return true if the specified TargetRegisterClass is a
153 /// proper super-class of this TargetRegisterClass.
154 bool hasSuperClass(const TargetRegisterClass *RC) const
    [all...]
  /external/llvm/lib/CodeGen/
TargetRegisterInfo.cpp 110 const TargetRegisterClass *
111 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
121 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
134 const TargetRegisterClass *
140 const TargetRegisterClass* BestRC = nullptr;
142 const TargetRegisterClass* RC = *I;
155 const TargetRegisterClass *RC, BitVector &R){
163 const TargetRegisterClass *RC) const {
167 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
185 const TargetRegisterClass *firstCommonClass(const uint32_t *A
    [all...]
RegisterCoalescer.h 22 class TargetRegisterClass;
57 const TargetRegisterClass *NewRC;
112 const TargetRegisterClass *getNewRC() const { return NewRC; }
  /external/llvm/lib/Target/Mips/
Mips16RegisterInfo.h 35 const TargetRegisterClass *RC,
38 const TargetRegisterClass *intRegClass(unsigned Size) const override;
MipsSERegisterInfo.h 31 const TargetRegisterClass *intRegClass(unsigned Size) const override;
MipsMachineFunction.cpp 41 const TargetRegisterClass *RC =
62 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
68 const TargetRegisterClass *RC =
83 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
106 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
  /external/llvm/lib/Target/WebAssembly/
WebAssemblyRegisterInfo.h 26 class TargetRegisterClass;
45 const TargetRegisterClass *
  /external/llvm/lib/Target/AArch64/
AArch64RegisterInfo.h 24 class TargetRegisterClass;
66 const TargetRegisterClass *
69 const TargetRegisterClass *
70 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
96 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
  /external/llvm/lib/Target/BPF/
BPFInstrInfo.h 40 const TargetRegisterClass *RC,
45 int FrameIndex, const TargetRegisterClass *RC,
  /external/llvm/lib/Target/NVPTX/
NVPTXRegisterInfo.h 60 std::string getNVPTXRegClassName(const TargetRegisterClass *RC);
61 std::string getNVPTXRegClassStr(const TargetRegisterClass *RC);
  /external/llvm/lib/Target/MSP430/
MSP430RegisterInfo.h 32 const TargetRegisterClass*

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