| /external/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 227 unsigned TmpReg = MRI.createVirtualRegister(NewSrcRC);
229 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY), TmpReg)
232 MI.getOperand(I).setReg(TmpReg);
|
| SIRegisterInfo.cpp | 384 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj);
386 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
388 FIOp.ChangeToRegister(TmpReg, false, false, true);
|
| SIInstrInfo.cpp | 680 RegScavenger *RS, unsigned TmpReg,
769 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
773 return TmpReg;
[all...] |
| SIInstrInfo.h | 106 unsigned TmpReg,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| PPCFrameLowering.cpp | [all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 290 unsigned TmpReg = MRI->createVirtualRegister(
293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
305 MIB.addReg(TmpReg, getKillRegState(true))
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| ThumbRegisterInfo.cpp | 572 unsigned TmpReg = MI.getOperand(0).getReg();
576 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
579 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
583 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
588 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 568 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
577 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
582 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
583 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
|
| MipsFastISel.cpp | 319 unsigned TmpReg = createResultReg(RC);
320 emitInst(Mips::LUi, TmpReg).addImm(Hi);
321 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 266 unsigned BaseReg, IndexReg, TmpReg, Scale;
276 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
387 BaseReg = TmpReg;
390 IndexReg = TmpReg;
424 BaseReg = TmpReg;
427 IndexReg = TmpReg;
457 TmpReg = Reg;
514 IndexReg = TmpReg;
603 BaseReg = TmpReg;
606 IndexReg = TmpReg;
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 380 unsigned TmpReg = createResultReg(RC);
381 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg)
387 .addReg(TmpReg, getKillRegState(true));
[all...] |
| /external/llvm/lib/CodeGen/ |
| TwoAddressInstructionPass.cpp | 338 unsigned TmpReg = FromReg;
340 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI);
344 TmpReg = Def->getOperand(1).getReg();
346 if (TmpReg == ToReg)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
