| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 405 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
409 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
413 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
417 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
422 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
426 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
430 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
434 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
|
| ARMISelLowering.cpp | 143 setOperationAction(ISD::UREM, VT, Expand);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 41 setOperationAction(ISD::UREM, MVT::i32, Expand);
|
| AMDILISelLowering.cpp | 118 // TODO: Implement custom UREM/SREM routines
725 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
|
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | [all...] |
| MipsSEISelLowering.cpp | 171 setOperationAction(ISD::UREM, MVT::i32, Legal);
218 setOperationAction(ISD::UREM, MVT::i64, Legal);
273 setOperationAction(ISD::UREM, Ty, Legal);
[all...] |
| MipsISelLowering.cpp | 317 setOperationAction(ISD::UREM, MVT::i32, Expand);
321 setOperationAction(ISD::UREM, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 152 setOperationAction(ISD::UREM, MVT::i8, Expand);
158 setOperationAction(ISD::UREM, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 781 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
[all...] |
| SelectionDAGDumper.cpp | 183 case ISD::UREM: return "urem";
|
| FastISel.cpp | 438 // Transform "urem x, pow2" -> "and x, pow2-1".
439 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
[all...] |
| LegalizeVectorOps.cpp | 267 case ISD::UREM:
[all...] |
| LegalizeVectorTypes.cpp | 128 case ISD::UREM:
684 case ISD::UREM:
[all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 125 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
[all...] |
| LegalizeDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 120 setOperationAction(ISD::UREM, MVT::i64, Expand);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 273 setOperationAction(ISD::UREM, MVT::i32, Expand);
314 setOperationAction(ISD::UREM, VT, Expand);
[all...] |
| SIISelLowering.cpp | 193 setOperationAction(ISD::UREM, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
