/external/llvm/include/llvm/MC/ |
MCInstrItineraries.h | 185 /// operand index UseIdx. 187 unsigned UseClass, unsigned UseIdx) const { 197 if ((FirstUseIdx + UseIdx) >= LastUseIdx) 201 Forwardings[FirstUseIdx + UseIdx]; 208 unsigned UseClass, unsigned UseIdx) const { 216 int UseCycle = getOperandCycle(UseClass, UseIdx); 222 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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MCSubtargetInfo.h | 135 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, 142 if (I->UseIdx < UseIdx) 144 if (I->UseIdx > UseIdx)
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MCSchedule.h | 84 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by 87 unsigned UseIdx; 92 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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/external/llvm/lib/CodeGen/ |
TargetSchedule.cpp | 144 unsigned UseIdx = 0; 148 ++UseIdx; 150 return UseIdx; 202 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); 203 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
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LiveRangeEdit.cpp | 81 /// OrigIdx are also available with the same value at UseIdx. 84 SlotIndex UseIdx) const { 86 UseIdx = UseIdx.getRegSlot(true); 107 if (SlotIndex::isSameInstr(OrigIdx, UseIdx)) 110 if (OVNI != li.getVNInfoAt(UseIdx)) 117 SlotIndex UseIdx, 140 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
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LiveRangeCalc.cpp | 170 SlotIndex UseIdx; 175 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB()); 187 UseIdx = Indexes->getInstructionIndex(MI).getRegSlot(isEarlyClobber); 192 extend(LR, UseIdx, Reg);
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SplitKit.h | 315 /// defFromParent - Define Reg from ParentVNI at UseIdx using either 319 SlotIndex UseIdx,
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InlineSpiller.cpp | 867 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); 868 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); 877 DEBUG(dbgs() << UseIdx << '\t' << *MI); [all...] |
TargetInstrInfo.cpp | [all...] |
RegisterCoalescer.cpp | 695 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); 696 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); 749 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true); 750 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); 770 SlotIndex DefIdx = UseIdx.getRegSlot(); [all...] |
MachineVerifier.cpp | [all...] |
MachineInstr.cpp | [all...] |
TwoAddressInstructionPass.cpp | 416 SlotIndex useIdx = LIS->getInstructionIndex(MI); 417 LiveInterval::const_iterator I = LI.find(useIdx); 419 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx); [all...] |
SplitKit.cpp | 421 SlotIndex UseIdx, 434 if (Edit->canRematerializeAt(RM, UseIdx, true)) { [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.h | 287 unsigned UseIdx) const override; 290 SDNode *UseNode, unsigned UseIdx) const override; 319 unsigned UseIdx, unsigned UseAlign) const; 323 unsigned UseIdx, unsigned UseAlign) const; 328 unsigned UseIdx, unsigned UseAlign) const; 343 unsigned UseIdx) const override;
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ARMBaseInstrInfo.cpp | [all...] |
/external/llvm/include/llvm/CodeGen/ |
LiveRangeEdit.h | 87 /// OrigIdx are also available with the same value at UseIdx. 89 SlotIndex UseIdx) const; 183 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI. 186 SlotIndex UseIdx,
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MachineInstr.h | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.h | 122 unsigned UseIdx) const override; 125 SDNode *UseNode, unsigned UseIdx) const override { 127 UseNode, UseIdx);
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PPCVSXSwapRemoval.cpp | 672 int UseIdx = SwapMap[&UseMI]; 674 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad || 675 SwapVector[UseIdx].IsStore) { 683 DEBUG(dbgs() << " use " << UseIdx << ": "); 736 int UseIdx = SwapMap[&UseMI]; 737 SwapVector[UseIdx].WillRemove = 1; [all...] |
PPCInstrInfo.cpp | 143 unsigned UseIdx) const { 145 UseMI, UseIdx); [all...] |
/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | [all...] |
/external/llvm/utils/TableGen/ |
SubtargetEmitter.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 486 unsigned UseIdx) const override;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | [all...] |