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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/
addsub.s 178 do_extend 0, \op, WSP, W
185 do_extend 1, \op, WSP, W
192 do_extend 2, \op, WSP, W
  /art/runtime/arch/arm64/
registers_arm64.h 105 WSP = 31,
  /external/llvm/lib/Target/AArch64/
AArch64RegisterInfo.cpp 111 Reserved.set(AArch64::WSP);
141 case AArch64::WSP:
AArch64InstrInfo.cpp     [all...]
  /art/compiler/utils/arm64/
assembler_arm64.h 238 if (code == WSP) {
239 return vixl::wsp;
managed_register_arm64_test.cc     [all...]
  /art/compiler/optimizing/
common_arm64.h 32 static_assert((SP == 31) && (WSP == 31) && (XZR == 32) && (WZR == 32),
246 // only SP/WSP and ZXR/WZR codes are different between art and vixl.
  /external/llvm/lib/Target/AArch64/InstPrinter/
AArch64InstPrinter.cpp     [all...]
  /external/llvm/lib/Target/AArch64/Utils/
AArch64BaseInfo.h 63 case AArch64::SP: return AArch64::WSP;
103 case AArch64::WSP: return AArch64::SP;
    [all...]
  /external/llvm/test/MC/AArch64/
arm64-aliases.s 5 ; ADD #0 to/from SP/WSP is a MOV
11 add w3, wsp, #0
12 ; CHECK: mov w3, wsp
13 add wsp, w4, #0
14 ; CHECK: mov wsp, w4
19 mov w7, wsp
20 ; CHECK: mov w7, wsp
21 mov wsp, w8
22 ; CHECK: mov wsp, w8
93 cmp wsp, w9, lsl #
    [all...]
  /external/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp 430 Register = AArch64::WSP;
    [all...]
  /toolchain/binutils/binutils-2.25/opcodes/
aarch64-tbl.h 131 /* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}. */
139 /* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP. */
142 QLF2(WSP,W), \
143 QLF2(W,WSP), \
    [all...]
  /toolchain/binutils/binutils-2.25/gas/config/
tc-aarch64.c 282 BASIC_REG_TYPE(SP_32) /* wsp */ \
    [all...]

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