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  /device/google/contexthub/firmware/src/platform/stm32f4xx/
wdt.c 30 #define WWDG ((struct StmWwdg*)WWDG_BASE)
32 /* WWDG bit definitions */
43 /* WWDG parameters */
78 WWDG->CFR = WWDG_CFR_EWI | WWDG_CFR_DIV8 | WWDG_TCNT_HIGH | (WWDG_WINDOW_SIZE & WWDG_TCNT_MASK);
79 WWDG->CR = WWDG_CR_ENABLE | WWDG_TCNT_HIGH | (WWDG_WINDOW_SIZE & WWDG_TCNT_MASK);
80 // with 16Mhz APB1 clock, this is 256*DIV = 2,048 uS per WWDG tick with DIV=8, max 131,072 uS WWDG window
86 WWDG->CR = (WWDG->CR & ~WWDG_TCNT_MASK) | WWDG_TCNT_HIGH | (WWDG_WINDOW_SIZE & WWDG_TCNT_MASK);
crt_stm32f4xx.c 41 VECI(WWDG);

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