| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68k/ |
| br-isab.d | 12 2: 61ff ffff fffc bsrl 0 <foo>
17 12: 61ff 0000 0000 bsrl 14 <foo\+0x14>
|
| br-isac.d | 12 2: 61ff ffff fffc bsrl 0 <foo>
19 18: 61ff 0000 0000 bsrl 1a <foo\+0x1a>
|
| pcrel.s | 17 bsrl lbl_a
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-m68k/ |
| plt1-isac.d | 22 2082a: 61ff ffff ffd4 bsrl 20800 <f.@plt-0x18>
30 20842: 61ff ffff ffbc bsrl 20800 <f.@plt-0x18>
38 2085a: 61ff ffff ffa4 bsrl 20800 <f.@plt-0x18>
42 20c00: 61ff ffff fc.. bsrl 208.. <f1@plt>
43 20c06: 61ff ffff fc.. bsrl 208.. <f2@plt>
44 20c0c: 61ff ffff fc.. bsrl 208.. <f3@plt>
|
| plt1-68020.d | 33 20c00: 61ff ffff fc.. bsrl 208.. <f1@plt>
34 20c06: 61ff ffff fc.. bsrl 208.. <f2@plt>
35 20c0c: 61ff ffff fc.. bsrl 208.. <f3@plt>
|
| plt1-cpu32.d | 41 20c00: 61ff ffff fc.. bsrl 208.. <f1@plt>
42 20c06: 61ff ffff fc.. bsrl 208.. <f2@plt>
43 20c0c: 61ff ffff fc.. bsrl 208.. <f3@plt>
|
| plt1-isab.d | 42 20c00: 61ff ffff fc.. bsrl 208.. <f1@plt>
43 20c06: 61ff ffff fc.. bsrl 208.. <f2@plt>
44 20c0c: 61ff ffff fc.. bsrl 208.. <f3@plt>
|
| /external/compiler-rt/lib/builtins/i386/ |
| udivdi3.S | 27 bsrl %ebx, %ecx // If the high word of b is zero, jump to
|
| umoddi3.S | 28 bsrl %ebx, %ecx // If the high word of b is zero, jump to
|
| divdi3.S | 56 bsrl %ebx, %ecx // If the high word of b is zero, jump to
|
| moddi3.S | 55 bsrl %ebx, %ecx // If the high word of b is zero, jump to
|
| /art/compiler/utils/x86/ |
| assembler_x86_test.cc | 253 TEST_F(AssemblerX86Test, Bsrl) {
254 DriverStr(RepeatRR(&x86::X86Assembler::bsrl, "bsrl %{reg2}, %{reg1}"), "bsrl");
258 GetAssembler()->bsrl(x86::Register(x86::EDI), x86::Address(
261 "bsrl 0xc(%EDI,%EBX,4), %EDI\n";
|
| assembler_x86.h | 339 void bsrl(Register dst, Register src);
340 void bsrl(Register dst, const Address& src);
|
| assembler_x86.cc | 175 void X86Assembler::bsrl(Register dst, Register src) { function in class:art::x86::X86Assembler
182 void X86Assembler::bsrl(Register dst, const Address& src) { function in class:art::x86::X86Assembler
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| microblaze-opcm.h | 31 idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, enumerator in enum:microblaze_instr
|
| microblaze-opc.h | 148 {"bsrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst },
[all...] |
| /art/compiler/utils/x86_64/ |
| assembler_x86_64_test.cc | [all...] |
| assembler_x86_64.h | 648 void bsrl(CpuRegister dst, CpuRegister src);
649 void bsrl(CpuRegister dst, const Address& src);
[all...] |
| assembler_x86_64.cc | 2231 void X86_64Assembler::bsrl(CpuRegister dst, CpuRegister src) { function in class:art::x86_64::X86_64Assembler
2239 void X86_64Assembler::bsrl(CpuRegister dst, const Address& src) { function in class:art::x86_64::X86_64Assembler
[all...] |
| /external/valgrind/VEX/test/ |
| test-amd64.c | 560 TEST_BSX(bsrl, "", 0);
561 TEST_BSX(bsrl, "", 0x00340128);
[all...] |
| test-i386.c | 522 TEST_BSX(bsrl, "", 0);
523 TEST_BSX(bsrl, "", 0x00340128);
[all...] |
| /external/v8/test/cctest/ |
| test-disasm-x64.cc | 91 __ bsrl(rax, r15);
92 __ bsrl(r9, Operand(rcx, times_8, 91919));
|
| /art/compiler/optimizing/ |
| intrinsics_x86.cc | [all...] |
| intrinsics_x86_64.cc | [all...] |
| /external/v8/src/x64/ |
| assembler-x64.h | [all...] |
