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Searched
refs:clobbersPhysReg
(Results
1 - 25
of
26
) sorted by null
1
2
/external/llvm/lib/Target/X86/
X86VZeroUpper.cpp
119
if (!MO.
clobbersPhysReg
(reg))
149
if (MO.
clobbersPhysReg
(reg))
X86RegisterInfo.cpp
418
if (MachineOperand::
clobbersPhysReg
(RegMask, getBaseRegister()))
X86FrameLowering.cpp
[
all
...]
/external/llvm/include/llvm/CodeGen/
MachineOperand.h
471
///
clobbersPhysReg
- Returns true if this RegMask clobbers PhysReg.
475
static bool
clobbersPhysReg
(const uint32_t *RegMask, unsigned PhysReg) {
481
///
clobbersPhysReg
- Returns true if this RegMask operand clobbers PhysReg.
482
bool
clobbersPhysReg
(unsigned PhysReg) const {
483
return
clobbersPhysReg
(getRegMask(), PhysReg);
/external/llvm/lib/CodeGen/
LivePhysRegs.cpp
33
if (MO.
clobbersPhysReg
(*LRI)) {
InterferenceCache.cpp
187
if (MachineOperand::
clobbersPhysReg
(RegMaskBits[i], PhysReg)) {
244
if (MachineOperand::
clobbersPhysReg
(RegMaskBits[i-1], PhysReg)) {
CriticalAntiDepBreaker.cpp
252
if (MO.
clobbersPhysReg
(i)) {
348
if (CheckOper.isRegMask() && CheckOper.
clobbersPhysReg
(NewReg))
MachineCopyPropagation.cpp
282
if (MRI->isReserved(Reg) || !MaskMO.
clobbersPhysReg
(Reg))
MachineInstrBundle.cpp
303
if (MO.isRegMask() && MO.
clobbersPhysReg
(Reg)) {
ShrinkWrap.cpp
241
if (MO.
clobbersPhysReg
(Reg)) {
RegisterScavenging.cpp
117
if (MO.
clobbersPhysReg
(*RURI)) {
LiveVariables.cpp
431
if (!MO.
clobbersPhysReg
(Reg))
437
if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.
clobbersPhysReg
(*SR))
MachineCSE.cpp
191
if (MO.isRegMask() && MO.
clobbersPhysReg
(Reg))
PeepholeOptimizer.cpp
[
all
...]
MachineInstr.cpp
[
all
...]
MachineVerifier.cpp
[
all
...]
RegisterCoalescer.cpp
[
all
...]
/external/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp
576
if (U.
clobbersPhysReg
(J.first))
713
if (MO.
clobbersPhysReg
(I->first)) {
AArch64CollectLOH.cpp
335
if (MachineOperand::
clobbersPhysReg
(PreservedRegs, Entry.first)) {
[
all
...]
AArch64InstrInfo.cpp
916
if (MO.isRegMask() && MO.
clobbersPhysReg
(AArch64::NZCV)) {
[
all
...]
/external/llvm/lib/Target/PowerPC/
PPCCTRLoops.cpp
597
if (MO.
clobbersPhysReg
(PPC::CTR) || MO.
clobbersPhysReg
(PPC::CTR8))
PPCInstrInfo.cpp
[
all
...]
/external/llvm/lib/Target/ARM/
ThumbRegisterInfo.cpp
475
if (MO.isRegMask() && MO.
clobbersPhysReg
(ARM::R12)) {
ARMBaseInstrInfo.cpp
509
if ((MO.isRegMask() && MO.
clobbersPhysReg
(ARM::CPSR)) ||
[
all
...]
/external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGRRList.cpp
[
all
...]
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