/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
r6-64-removed.s | 4 ddivu $2, $4
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vr4120-2.s | 30 ddivu $0,$7,$8 34 ddivu $0,$7,$8 121 ddivu $0,$4,$5 145 ddivu $0,$4,$5
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r6-64-removed.l | 4 .*:4: Error: invalid operands `ddivu \$2,\$4'
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r6-64.s | 8 ddivu $2,$3,$4
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vr4120-2.d | 34 .* <[^>]*> ddivu zero,a3,t0 38 .* <[^>]*> ddivu zero,a3,t0 138 .* <[^>]*> ddivu zero,a0,a1 168 .* <[^>]*> ddivu zero,a0,a1
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div.s | 35 ddivu $4,$5,2
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mips16-macro.s | 7 ddivu $5,$6,$7
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div-ilocks.d | 102 0+0170 <[^>]*> ddivu zero,a1,at 108 0+0188 <[^>]*> ddivu zero,a1,at
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div.d | 115 0+01a8 <[^>]*> ddivu zero,a1,at 123 0+01c8 <[^>]*> ddivu zero,a1,at
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r6-64-n32.d | 17 0+0018 <[^>]*> 0064109f ddivu v0,v1,a0
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mips16-macro.d | 23 [ 0-9a-f]+: eeff ddivu \$0,\$6,\$7 39 [ 0-9a-f]+: ecbf ddivu \$0,\$4,\$5
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r6-64-n64.d | 17 0+0018 <[^>]*> 0064109f ddivu v0,v1,a0
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vr4130.s | 323 check3 ddivu
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mips16.s | 206 ddivu $2,$3
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vr4130.d | 357 .* ddivu .* 838 .* ddivu .*
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loongson-2e.s | 17 ddivu.g $23, $24, $25
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loongson-2f.s | 17 ddivu.g $23, $24, $25
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/external/llvm/test/MC/Mips/ |
macro-ddivu.s | 6 ddivu $25,$11 8 # CHECK-NOTRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f] 12 ddivu $24,$12 14 # CHECK-NOTRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f] 18 ddivu $25,$0 20 # CHECK-NOTRAP: ddivu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1f] 24 ddivu $0,$9 26 # CHECK-NOTRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f] 30 ddivu $0,$0 32 # CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f [all...] |
macro-ddivu-bad.s | 11 ddivu $25, $11 14 ddivu $25, $0 17 ddivu $0,$0
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/external/llvm/test/MC/Mips/micromips64r6/ |
invalid.s | 72 ddivu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 73 ddivu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 74 ddivu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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valid.s | 32 ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0x64,0x29,0x98]
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/external/v8/test/cctest/ |
test-disasm-mips64.cc | 228 COMPARE(ddivu(a0, a1), 229 "0085001f ddivu a0, a1"); 230 COMPARE(ddivu(a6, a7), 231 "014b001f ddivu a6, a7"); 232 COMPARE(ddivu(v0, v1), 233 "0043001f ddivu v0, v1"); 320 COMPARE(ddivu(a0, a1, a2), 321 "00a6209f ddivu a0, a1, a2"); 328 COMPARE(ddivu(a5, a6, a7), 329 "014b489f ddivu a5, a6, a7") [all...] |
/external/llvm/test/MC/Mips/mips64r6/ |
invalid-mips3.s | 31 # ddivu has been re-encoded. See valid.s
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invalid-mips64.s | 52 # ddivu has been re-encoded. See valid.s
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/external/llvm/test/MC/Mips/mips1/ |
invalid-mips3.s | 25 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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