/external/llvm/test/MC/Mips/ |
set-mips-directives.s | 31 drotr32 $1,$14,15 34 drotr32 $1,$14,15 37 drotr32 $1,$14,15 67 # CHECK: drotr32 $1, $14, 15 70 # CHECK: drotr32 $1, $14, 15 73 # CHECK: drotr32 $1, $14, 15
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set-arch.s | 30 drotr32 $1, $14, 15 33 drotr32 $1, $14, 15 36 drotr32 $1, $14, 15 62 # CHECK: drotr32 $1, $14, 15
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rotations64.s | 108 # CHECK-64R: drotr32 $4, $4, 31 # encoding: [0x00,0x24,0x27,0xfe] 116 # CHECK-64R: drotr32 $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfe] 121 # CHECK-64R: drotr32 $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7e] 126 # CHECK-64R: drotr32 $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3e] 144 # CHECK-64R: drotr32 $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfe] 149 # CHECK-64R: drotr32 $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7e] 154 # CHECK-64R: drotr32 $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3e] 200 # CHECK-64R: drotr32 $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3e] 205 # CHECK-64R: drotr32 $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7e] 210 # CHECK-64R: drotr32 $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfe [all...] |
set-mips-directives-bad.s | 33 drotr32 $1,$14,15 # CHECK: error: instruction requires a CPU feature not currently enabled
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mips64-alu-instructions.s | 77 # CHECK: drotr32 $9, $6, 20 # encoding: [0x3e,0x4d,0x26,0x00] 102 drotr32 $9, $6, 20
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/external/llvm/test/MC/Mips/mips64/ |
invalid-mips64r2.s | 11 drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 12 drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
mips64r2.s | 55 drotr32 $25, $10, 4 # dror32
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micromips.s | [all...] |
/external/llvm/test/MC/Mips/mips5/ |
invalid-mips64r2.s | 16 drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 17 drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/art/runtime/interpreter/mterp/mips64/ |
header.S | 239 drotr32 \reg, \reg, 0
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/external/llvm/test/MC/Mips/mips64r2/ |
valid.s | 98 drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfe] 99 drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfe]
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/external/llvm/test/MC/Mips/mips64r3/ |
valid.s | 98 drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfe] 99 drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfe]
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/external/llvm/test/MC/Mips/mips64r5/ |
valid.s | 98 drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfe] 99 drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfe]
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/external/v8/test/cctest/ |
test-disasm-mips64.cc | 540 COMPARE(drotr32(a0, a1, 0), "0025203e drotr32 a0, a1, 0"); 541 COMPARE(drotr32(s0, s1, 8), "0031823e drotr32 s0, s1, 8"); 542 COMPARE(drotr32(a6, a7, 24), "002b563e drotr32 a6, a7, 24"); 543 COMPARE(drotr32(v0, v1, 31), "002317fe drotr32 v0, v1, 31"); [all...] |
/external/v8/src/mips64/ |
disasm-mips64.cc | [all...] |
assembler-mips64.h | 795 void drotr32(Register rd, Register rt, uint16_t sa); [all...] |
assembler-mips64.cc | 1880 void Assembler::drotr32(Register rd, Register rt, uint16_t sa) { function in class:v8::internal::Assembler [all...] |
macro-assembler-mips64.cc | [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
mips-opc.c | [all...] |
/art/runtime/interpreter/mterp/out/ |
mterp_mips64.S | 246 drotr32 \reg, \reg, 0 [all...] |