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    Searched refs:hasSubClassEq (Results 1 - 17 of 17) sorted by null

  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 189 if (Mips::GPR32RegClass.hasSubClassEq(RC))
191 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
193 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
195 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
197 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
199 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
201 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
203 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
205 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
215 else if (Mips::LO32RegClass.hasSubClassEq(RC)
    [all...]
Mips16InstrInfo.cpp 103 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
122 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 706 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
707 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
708 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
709 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
739 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
740 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
742 PPC::GPRCRegClass.hasSubClassEq(RC) ||
743 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
    [all...]
PPCVSXCopy.cpp 60 return RC->hasSubClassEq(MRI.getRegClass(Reg));
PPCVSXSwapRemoval.cpp 166 return RC->hasSubClassEq(MRI->getRegClass(Reg));
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 302 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
376 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
377 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
390 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
391 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
736 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
    [all...]
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 143 return RC != this && hasSubClassEq(RC);
147 bool hasSubClassEq(const TargetRegisterClass *RC) const {
160 return RC->hasSubClassEq(this);
164 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcInstrInfo.cpp 396 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
399 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
434 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
437 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
SparcISelLowering.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 862 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
866 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
874 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
878 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
899 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
916 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
    [all...]
Thumb2InstrInfo.cpp 147 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
186 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
ThumbRegisterInfo.cpp 49 if (ARM::tGPRRegClass.hasSubClassEq(RC))
  /external/llvm/lib/Target/X86/
X86InstrInfo.cpp     [all...]
  /external/llvm/lib/CodeGen/
MachineFunction.cpp 479 RC->hasSubClassEq(VRegRC))) &&
    [all...]
TargetInstrInfo.cpp 425 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 552 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 716 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
720 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
724 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
    [all...]

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