/toolchain/binutils/binutils-2.25/gas/testsuite/gas/score/ |
b.s | 8 .macro tran insn32, insn16 12 \insn32 #32b -> 16b 15 \insn32 #32b -> 16b 16 \insn32 #32b -> 16b 19 \insn32 #32b -> 16b 21 \insn32 #No transform
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br.s | 10 .macro tran3216 insn32, insn16 13 \insn32 r0 #32b -> 16b 16 \insn32 r15 #32b -> 16b 19 \insn32 r3 #32b -> 16b 20 \insn32 r3 #32b -> 16b 23 \insn32 r5 #32b -> 16b 25 \insn32 r3 #No transform 26 \insn32 r31 #No transform 31 .macro tran1632 insn32, insn16 35 \insn32 r23 [all...] |
ldi.s | 11 .macro tran3216 insn32, insn16 14 \insn32 r2, 0 #32b -> 16b 17 \insn32 r3, 255 #32b -> 16b 20 \insn32 r4, 9 #32b -> 16b 21 \insn32 r4, 9 #32b -> 16b 24 \insn32 r3, 255 #32b -> 16b 26 \insn32 r8, 3 #No transform 27 \insn32 r25, 3 #No transform 33 .macro tran1632 insn32, insn16 37 \insn32 r25, 0 [all...] |
bittst.s | 9 .macro tran3216 insn32, insn16 11 \insn32 r0, 2 #32b -> 16b 14 \insn32 r15, 4 #32b -> 16b 17 \insn32 r15, 1 #32b -> 16b 21 \insn32 r15, 3 #32b -> 16b 23 \insn32 r8, 2 #32b -> 16b 24 \insn32 r8, 2 #32b -> 16b 26 \insn32 r15, 1 #No transform 27 \insn32 r26, 4 32 .macro tran1632 insn32, insn1 [all...] |
postlw.s | 12 .macro tran3216 insn32, insn16 15 \insn32 r23, [r7]+, 4 #32b -> 16b 18 \insn32 r0, [r2]+, 4 #32b -> 16b 21 \insn32 r15, [r0]+, 4 #32b -> 16b 25 \insn32 r15, [r7]+, 4 #32b -> 16b 27 \insn32 r25, [r3]+, 4 #32b -> 16b 28 \insn32 r25, [r3]+, 4 #32b -> 16b 30 \insn32 r24, [r13]+, 4 #No transform 31 \insn32 r23, [r7]+, 5 #No transform 36 .macro tran1632 insn32, insn1 [all...] |
presw.s | 12 .macro tran3216 insn32, insn16 15 \insn32 r0, [r2, -4]+ #32b -> 16b 18 \insn32 r23, [r7, -4]+ #32b -> 16b 21 \insn32 r15, [r0, -4]+ #32b -> 16b 25 \insn32 r15, [r7, -4]+ #32b -> 16b 27 \insn32 r25, [r3, -4]+ #32b -> 16b 28 \insn32 r25, [r3, -4]+ #32b -> 16b 30 \insn32 r24, [r13, -4]+ #No transform 31 \insn32 r23, [r7, -5]+ #No transform 36 .macro tran1632 insn32, insn1 [all...] |
nop.s | 8 .macro tran insn32, insn16 12 \insn32 #32b -> 16b 15 \insn32 #32b -> 16b 16 \insn32 #32b -> 16b 19 \insn32 #32b -> 16b 21 \insn32 #No transform 28 \insn32
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tcond.s | 9 .macro tran insn32, insn16 13 \insn32 #32b -> 16b 16 \insn32 #32b -> 16b 17 \insn32 #32b -> 16b 20 \insn32 #32b -> 16b 22 \insn32 #No transform 29 \insn32
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rD_rA.s | 11 .macro tran3216 insn32, insn16 14 \insn32 r0, r7 #32b -> 16b 17 \insn32 r15, r4 #32b -> 16b 20 \insn32 r15, r15 #32b -> 16b 24 \insn32 r15, r3 #32b -> 16b 26 \insn32 r8, r2 #32b -> 16b 27 \insn32 r8, r2 #32b -> 16b 29 \insn32 r15, r5 #No transform 30 \insn32 r26, r23 35 .macro tran1632 insn32, insn1 [all...] |
rD_rA_BN.s | 13 .macro tran3216 insn32, insn16 16 \insn32 r0, r0, 2 #32b -> 16b 19 \insn32 r15, r15, 4 #32b -> 16b 22 \insn32 r15, r15, 1 #32b -> 16b 26 \insn32 r15, r15, 3 #32b -> 16b 28 \insn32 r8, r8, 3 #32b -> 16b 29 \insn32 r8, r8, 3 #32b -> 16b 31 \insn32 r15, r15, 1 #No transform 32 \insn32 r26, r23, 4 37 .macro tran1632 insn32, insn1 [all...] |
rD_rA_rB.s | 18 .macro tran3216 insn32, insn16 21 \insn32 r0, r0, r2 #32b -> 16b 24 \insn32 r5, r5, r4 #32b -> 16b 27 \insn32 r15, r15, r4 #32b -> 16b 31 \insn32 r15, r15, r3 #32b -> 16b 33 \insn32 r8, r8, r3 #32b -> 16b 34 \insn32 r8, r8, r3 #32b -> 16b 36 \insn32 r15, r15, r6 #No transform 37 \insn32 r26, r23, r4 42 .macro tran1632 insn32, insn1 [all...] |
ls32ls16p.s | 14 .macro tran3216 insn32, insn16, shift 17 \insn32 r3, [r2, 0x4 << \shift] #32b -> 16b 20 \insn32 r4, [r2, 0xC << \shift] #32b -> 16b 23 \insn32 r7, [r2, 0x12 << \shift] #32b -> 16b 24 \insn32 r7, [r2, 0x12 << \shift] #32b -> 16b 27 \insn32 r8, [r2, 0x8 << \shift] #32b -> 16b 29 \insn32 r5, [r2, 0x20 << \shift] #No transform 30 \insn32 r5, [r2, 0x20 << \shift] #No transform 32 \insn32 r6, [r6, 0x8 << \shift] #No transform 33 \insn32 r6, [r6, 0x8 << \shift] #No transfor [all...] |
ls32ls16.s | 14 .macro tran3216 insn32, insn16 17 \insn32 r0, [r3, 0] #32b -> 16b 20 \insn32 r3, [r15, 0] #32b -> 16b 23 \insn32 r15, [r8, 0] #32b -> 16b 26 \insn32 r4, [r8, 0] #No transform 27 \insn32 r25, [r19, 0] 29 \insn32 r5, [r7, 0] #32b -> 16b 30 \insn32 r5, [r7, 0] #32b -> 16b 33 \insn32 r2, [r3, 0] #32b -> 16b 38 .macro tran1632 insn32, insn1 [all...] |
addi.s | 14 .macro tran1632 insn32, insn16, sign 18 \insn32 r0, \sign * 1 21 \insn32 r15, \sign * 16 24 \insn32 r15, \sign * 1024 * 16 30 \insn32 r15, 0x7FFF
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relaxation_macro.h | 19 /* insn32/insn16 may include special characters, for example, blank character */ 20 .macro tran_16_32 insn16 insn32 21 _tran "\insn16", "\insn32" 29 .macro insn_32 insn32 31 \insn32
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
micromips.l | 2 .*:39: Error: opcode not supported in the `insn32' mode `nop16' 3 .*:98: Error: opcode not supported in the `insn32' mode `move16 \$2,\$22' 4 .*:99: Error: opcode not supported in the `insn32' mode `move16 \$22,\$2' 5 .*:106: Error: opcode not supported in the `insn32' mode `b16 test' 6 .*:111: Error: opcode not supported in the `insn32' mode `b16 1f' 7 .*:117: Error: opcode not supported in the `insn32' mode `b16 1b' 8 .*:277: Error: opcode not supported in the `insn32' mode `and16 \$2,\$2,\$3' 9 .*:315: Error: opcode not supported in the `insn32' mode `andi16 \$7,65535' 10 .*:387: Error: opcode not supported in the `insn32' mode `beqz16 \$16,test2' 11 .*:475: Error: opcode not supported in the `insn32' mode `bnez16 \$16,test3 [all...] |
micromips.s | 38 .ifndef insn32 97 .ifndef insn32 105 .ifndef insn32 110 .ifndef insn32 116 .ifndef insn32 276 .ifndef insn32 314 .ifndef insn32 386 .ifndef insn32 474 .ifndef insn32 [all...] |
micromips-insn32.d | 2 #name: microMIPS for MIPS32r2 (insn32 mode) 3 #as: -mips32r2 -32 -mfp64 -minsn32 -EB --defsym insn32=1 [all...] |
micromips-noinsn32.d | 2 #name: microMIPS for MIPS32r2 (instructions valid in insn32 mode) 3 #as: -mips32r2 -32 -mfp64 -EB --defsym insn32=1 [all...] |
/toolchain/binutils/binutils-2.25/bfd/ |
coff-arm.c | 76 typedef unsigned long int insn32; typedef 988 static insn32 989 insert_thumb_branch (insn32 br_insn, int rel_off) 1083 static const insn32 a2t1_ldr_insn = 0xe59fc000; 1084 static const insn32 a2t2_bx_r12_insn = 0xe12fff1c; 1085 static const insn32 a2t3_func_addr_insn = 0x00000001; 1109 static const insn32 t2a3_b_insn = 0xea000000; 1115 static const insn32 t2a5_pop_insn = 0xe8bd4040; 1116 static const insn32 t2a6_bx_insn = 0xe12fff1e; [all...] |
elfxx-mips.c | 443 bfd_boolean insn32; member in struct:mips_elf_link_hash_table 13389 bfd_boolean insn32 = mips_elf_hash_table (link_info)->insn32; local [all...] |
elf32-arm.c | 2052 typedef unsigned long int insn32; typedef [all...] |
/external/llvm/lib/Target/XCore/Disassembler/ |
XCoreDisassembler.cpp | 755 uint32_t insn32; local 757 if (!readInstruction32(Bytes, Address, Size, insn32)) { 762 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
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/toolchain/binutils/binutils-2.25/gas/config/ |
tc-mips.c | 239 Changed by `.set insn32' and `.set noinsn32', and the -minsn32 240 and -mno-insn32 command line options. */ 241 bfd_boolean insn32; member in struct:mips_set_options 284 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, 295 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, 813 ? (mips_opts.insn32 \ 820 || (mips_opts.micromips && !mips_opts.insn32)) \ [all...] |
/external/valgrind/VEX/priv/ |
guest_arm_toIR.c | 21922 UInt insn32 = (INSN0(15,0) << 16) | INSN1(15,0); local 21934 { UInt insn32 = (INSN0(15,0) << 16) | INSN1(15,0); local [all...] |